From 42dc8026a8711315652936ffd334a4752bbd5d2e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 18 Nov 2015 15:59:42 +0000 Subject: [PATCH] ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLE The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not bit 0 set. Furthermore, the name is inconsistent with the other definitions so rename it to TTBR_INNER_NON_CACHEABLE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Include/Chipset/ArmV7Mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index f612154bad..7fafc888fe 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -23,7 +23,7 @@ #define TTBR_SHAREABLE BIT1 #define TTBR_NON_SHAREABLE 0 #define TTBR_INNER_CACHEABLE BIT0 -#define TTBR_NON_INNER_CACHEABLE BIT0 +#define TTBR_INNER_NON_CACHEABLE 0 #define TTBR_RGN_INNER_NON_CACHEABLE 0 #define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6 #define TTBR_RGN_INNER_WRITE_THROUGH BIT0 -- 2.39.2