From 5374d621c509cbdc22beef7f4cd3526b02c93243 Mon Sep 17 00:00:00 2001 From: Shifei Lu Date: Thu, 11 Jun 2015 02:16:41 +0000 Subject: [PATCH] Add definitions for Protected Region 1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu Reviewed-by: David Wei git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17617 6f19259b-4bc3-4df7-8a09-765794883524 --- .../SouthCluster/Include/PchRegs/PchRegsSpi.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h index 132c64b837..7062a09b1b 100644 --- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h @@ -1,6 +1,6 @@ /** -Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved +Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. @@ -62,6 +62,12 @@ Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable #define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12] +#define R_PCH_SPI_PR1 0x78 // Protected Region 1 Register +#define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable +#define B_PCH_SPI_PR1_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12] +#define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable +#define B_PCH_SPI_PR1_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12] + #define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits) #define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask #define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask -- 2.39.2