From 59d3fad32ec928d91be3d6fbc3a5aab3409b5f68 Mon Sep 17 00:00:00 2001
From: Star Zeng <star.zeng@intel.com>
Date: Wed, 2 Aug 2017 10:07:31 +0800
Subject: [PATCH] UefiCpuPkg SecCore: Fix operands of different size in bitwise
 operation

It is introduced by 9e9ca2100f22be29f1a53129d741f4305ff34a71.

Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
---
 UefiCpuPkg/SecCore/SecMain.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index e9e243ca05..173bbfcfcb 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -281,7 +281,7 @@ SecStartupPhase2(
     // will be built based on them in PEI phase.
     //
     SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
-    SecCoreData->PeiTemporaryRamSize &= ~0x07;
+    SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
   } else {
     //
     // No addition PPI, PpiList directly point to the common PPI list.
-- 
2.39.2