From 62436c2162f2201eb105169b414719705adb7e3e Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Tue, 10 Dec 2013 16:39:04 +0000 Subject: [PATCH] ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Include/Chipset/AArch64Mmu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index 7c9890331f..77a96ec637 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -102,12 +102,12 @@ #define TCR_TG0_4KB (0 << 14) -#define TCR_IPS_4GB (0UL << 32) -#define TCR_IPS_64GB (1UL << 32) -#define TCR_IPS_1TB (2UL << 32) -#define TCR_IPS_4TB (3UL << 32) -#define TCR_IPS_16TB (4UL << 32) -#define TCR_IPS_256TB (5UL << 32) +#define TCR_IPS_4GB (0ULL << 32) +#define TCR_IPS_64GB (1ULL << 32) +#define TCR_IPS_1TB (2ULL << 32) +#define TCR_IPS_4TB (3ULL << 32) +#define TCR_IPS_16TB (4ULL << 32) +#define TCR_IPS_256TB (5ULL << 32) #define TTBR_ASID_FIELD (48) -- 2.39.2