From 6c9a3d4233d78a04db5f25aeed254396740f4cae Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 21 Feb 2020 11:30:31 +0100 Subject: [PATCH] ArmPlatformPkg/PrePeiCore: replace set/way cache ops with by-VA ones Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the temporary RAM region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled, which will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Acked-by: Laszlo Ersek --- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 6 ++++-- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 1 + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 4f691d62cf..5202aa641e 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -8,6 +8,7 @@ **/ #include +#include #include #include @@ -59,13 +60,14 @@ CEntryPoint ( { // Data Cache enabled on Primary core when MMU is enabled. ArmDisableDataCache (); - // Invalidate Data cache - ArmInvalidateDataCache (); // Invalidate instruction cache ArmInvalidateInstructionCache (); // Enable Instruction Caches on all cores. ArmEnableInstructionCache (); + InvalidateDataCacheRange ((VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), + PcdGet32 (PcdCPUCorePrimaryStackSize)); + // // Note: Doesn't have to Enable CPU interface in non-secure world, // as Non-secure interface is already enabled in Secure world. diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf index 104c7da533..fb01dd1a11 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -44,6 +44,7 @@ [LibraryClasses] ArmLib ArmPlatformLib + CacheMaintenanceLib BaseLib DebugLib DebugAgentLib diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index ceb173d34f..e9eb092d3a 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -44,6 +44,7 @@ [LibraryClasses] ArmLib ArmPlatformLib + CacheMaintenanceLib BaseLib DebugLib DebugAgentLib -- 2.39.2