From 753d3d6f43b2c2bf2df67038608496663ff6e3aa Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Wed, 29 May 2019 11:51:44 +0200 Subject: [PATCH] Revert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching" This reverts commit 9a2e8d7c65ef7f39c6754d27e52954b616bc6628. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 Signed-off-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daude Acked-by: Ard Biesheuvel --- OvmfPkg/PlatformPei/Platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 9c013613a1..5e0a154842 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -181,7 +181,6 @@ MemMapInitialization ( TopOfLowRam = GetSystemMemorySizeBelow4gb (); PciExBarBase = 0; - PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // // The MMCONFIG area is expected to fall between the top of low RAM and @@ -193,6 +192,7 @@ MemMapInitialization ( PciBase = (UINT32)(PciExBarBase + SIZE_256MB); PciSize = 0xFC000000 - PciBase; } else { + PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; PciSize = 0xFC000000 - PciBase; } -- 2.39.2