From 75839f977d377eb24ab55f5245977412a82844d4 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Sun, 22 Sep 2019 11:52:48 +0200 Subject: [PATCH] OvmfPkg/PlatformPei: detect SMRAM at default SMBASE (for real) Now that the SMRAM at the default SMBASE is honored everywhere necessary, implement the actual detection. The (simple) steps are described in previous patch "OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register macros". Regarding CSM_ENABLE builds: according to the discussion with Jiewen at https://edk2.groups.io/g/devel/message/48082 http://mid.mail-archive.com/74D8A39837DF1E4DA445A8C0B3885C503F7C9D2F@shsmsx102.ccr.corp.intel.com if the platform has SMRAM at the default SMBASE, then we have to (a) either punch a hole in the legacy E820 map as well, in LegacyBiosBuildE820() [OvmfPkg/Csm/LegacyBiosDxe/LegacyBootSupport.c], (b) or document, or programmatically catch, the incompatibility between the "SMRAM at default SMBASE" and "CSM" features. Because CSM is out of scope for the larger "VCPU hotplug with SMM" feature, option (b) applies. Therefore, if the CSM is enabled in the OVMF build, then PlatformPei will not attempt to detect SMRAM at the default SMBASE, at all. This is approach (4) -- the most flexible one, for end-users -- from: http://mid.mail-archive.com/868dcff2-ecaa-e1c6-f018-abe7087d640c@redhat.com https://edk2.groups.io/g/devel/message/48348 Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek Message-Id: <20200129214412.2361-12-lersek@redhat.com> Reviewed-by: Ard Biesheuvel --- OvmfPkg/PlatformPei/MemDetect.c | 16 ++++++++++++++++ OvmfPkg/PlatformPei/PlatformPei.inf | 1 + 2 files changed, 17 insertions(+) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 8fdc9c2ed7..47dc9c5437 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -103,6 +103,22 @@ Q35SmramAtDefaultSmbaseInitialization ( ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID); mQ35SmramAtDefaultSmbase = FALSE; + if (FeaturePcdGet (PcdCsmEnable)) { + DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE not checked due to CSM\n", + __FUNCTION__)); + } else { + UINTN CtlReg; + UINT8 CtlRegVal; + + CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL); + PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY); + CtlRegVal = PciRead8 (CtlReg); + mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal == + MCH_DEFAULT_SMBASE_IN_RAM); + DEBUG ((DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__, + mQ35SmramAtDefaultSmbase ? "found" : "not found")); + } + PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase, mQ35SmramAtDefaultSmbase); ASSERT_RETURN_ERROR (PcdStatus); diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index 25229618ed..c51a6176aa 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -106,6 +106,7 @@ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress [FeaturePcd] + gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire [Ppis] -- 2.39.2