From 7e5a6e394c65a295a761162621c546b1fea0b280 Mon Sep 17 00:00:00 2001 From: Leendert van Doorn Date: Thu, 24 Mar 2016 15:30:05 -0500 Subject: [PATCH] ArmPkg: apply Cortex-A57 errata Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Ard Biesheuvel --- .../Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c index 135bd6b86d..3d39acd50c 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c @@ -40,12 +40,15 @@ ArmCpuSetup ( } // - // If CPU is CortexA57 r0p0 apply Errata: 806969 + // If CPU is CortexA57 r0p0 apply Errata workarounds // if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) == ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) { - // DisableLoadStoreWB - ArmSetCpuActlrBit (1ULL << 49); + + // Errata 806969: DisableLoadStoreWB (1ULL << 49) + // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (1ULL << 44) + // Errata 814670: disable DMB nullification (1ULL << 58) + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) ); } } -- 2.39.2