From 8a3a97814e5402840164cb53ad6bb12ed851c54e Mon Sep 17 00:00:00 2001 From: Maurice Ma Date: Thu, 26 May 2016 15:13:23 -0700 Subject: [PATCH] CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue The current PCI 64bit memory BAR size calculation in PciHostBridgeLib assumes all 32 bits in the upper BAR are fully writable. However, platform might only support partial address programming, such as 40bit PCI BAR address. In this case the complement cannot be used for size calculation. Instead, the lowest non-zero bit should be used for BAR size calculation. Cc: Prince Agyeman Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma Reviewed-by: Prince Agyeman --- .../Library/PciHostBridgeLib/PciHostBridgeSupport.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index a95ffcaf64..0f1c8cb1a2 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -193,6 +193,7 @@ PcatPciRootBridgeParseBars ( UINT32 UpperValue; UINT64 Mask; UINTN Offset; + UINTN LowBit; UINT64 Base; UINT64 Length; UINT64 Limit; @@ -262,7 +263,10 @@ PcatPciRootBridgeParseBars ( Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32); Length = Length | LShiftU64 ((UINT64) UpperValue, 32); - Length = (~Length) + 1; + if (Length != 0) { + LowBit = LowBitSet64 (Length); + Length = LShiftU64 (1ULL, LowBit); + } if ((Value & BIT3) == BIT3) { MemAperture = PMemAbove4G; -- 2.39.2