From 98fed08f9f55e623b8f95518f69e35aca9ff1541 Mon Sep 17 00:00:00 2001 From: Girish K S Date: Tue, 27 Aug 2013 09:17:20 +0000 Subject: [PATCH] SCR_EL3 is the control register for setting the security state modified the comment which can mislead. The "ldr r0, [r1]" is overrided with a immediate "mov ro, #3" instruction. This mov instruction will over write the contents of the ro register. So replacing 'mov' by 'orr' instruction would prevent to override the original value. This patch assumes mov is the right instruction to be retained Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14606 6f19259b-4bc3-4df7-8a09-765794883524 --- .../ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S b/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S index 24d5bb031d..f06106608a 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S +++ b/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/boot.S @@ -57,7 +57,7 @@ _start: b.ne start_ns // skip EL3 initialisation mov x0, #0x30 // RES1 - orr x0, x0, #(1 << 0) // Non-secure EL1 + orr x0, x0, #(1 << 0) // Non-secure bit orr x0, x0, #(1 << 8) // HVC enable orr x0, x0, #(1 << 10) // 64-bit EL2 msr scr_el3, x0 @@ -88,7 +88,7 @@ _start: 2: ldr x1, =GIC_CPU_BASE // GICC_CTLR ldr w0, [x1] - mov w0, #3 // EnableGrp0 | EnableGrp1 + orr w0, w0, #3 // EnableGrp0 | EnableGrp1 str w0, [x1] mov w0, #1 << 7 // allow NS access to GICC_PMR -- 2.39.2