From 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8 Mon Sep 17 00:00:00 2001 From: Ruiyu Ni Date: Tue, 26 Sep 2017 23:26:32 +0800 Subject: [PATCH] UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid The patch optimized the MTRR access code to skip the Base MSR access when the Mask MSR indicates the pair is invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 +++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index a7adbafae3..2fd1d0153e 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -449,10 +449,13 @@ MtrrGetVariableMtrrWorker ( for (Index = 0; Index < VariableMtrrCount; Index++) { if (MtrrSetting == NULL) { - VariableSettings->Mtrr[Index].Base = - AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); - VariableSettings->Mtrr[Index].Mask = - AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); + VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); + // + // Skip to read the Base MSR when the Mask.V is not set. + // + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); + } } else { VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base; VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask; @@ -2540,14 +2543,14 @@ MtrrSetVariableMtrrWorker ( ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr)); for (Index = 0; Index < VariableMtrrCount; Index++) { - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), - VariableSettings->Mtrr[Index].Base - ); - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), - VariableSettings->Mtrr[Index].Mask - ); + // + // Mask MSR is always updated since caller might need to invalidate the MSR pair. + // Base MSR is skipped when Mask.V is not set. + // + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask); + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base); + } } } @@ -2800,7 +2803,7 @@ MtrrDebugPrintAllMtrrsWorker ( } for (Index = 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++) { - if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) { // // If mask is not valid, then do not display range // -- 2.39.2