From 9e9ca2100f22be29f1a53129d741f4305ff34a71 Mon Sep 17 00:00:00 2001 From: Star Zeng Date: Fri, 28 Jul 2017 22:13:00 +0800 Subject: [PATCH] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned As HOB which has 8byte aligned requirement will be built based on them in PEI phase. Cc: Liming Gao Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng Reviewed-by: Jeff Fan Reviewed-by: Liming Gao --- UefiCpuPkg/SecCore/SecMain.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 077d0db49f..18b7782bb8 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -1,7 +1,7 @@ /** @file C functions in SEC - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -230,6 +230,12 @@ SecStartupPhase2( ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR); + // + // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement + // will be built based on them in PEI phase. + // + SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07); + SecCoreData->PeiTemporaryRamSize &= ~0x07; } else { // // No addition PPI, PpiList directly point to the common PPI list. -- 2.39.2