From a7b35aae13b2d69b9be68874f275f511b1367a5e Mon Sep 17 00:00:00 2001 From: Ian Chiu Date: Fri, 5 Nov 2021 17:46:09 +0800 Subject: [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bits REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3703 MMIO base address size will overflow while finding two or more Host controller in the system. Correct it and support 32 and 64 bits address space. Signed-off-by: Ian Chiu Reviewed-by: Hao A Wu Cc: Maggie Chu Cc: Ray Ni Cc: Hao A Wu --- .../Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 47 ++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c index 447a05b5b2..86f1529eec 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c @@ -76,6 +76,8 @@ InitializeUfsHcPeim ( UINT16 Device; UINT16 Function; UINT32 Size; + UINT64 MmioSize; + UINT32 BarAddr; UINT8 SubClass; UINT8 BaseClass; UFS_HC_PEI_PRIVATE_DATA *Private; @@ -106,6 +108,7 @@ InitializeUfsHcPeim ( Private->PpiList = mPpiList; Private->PpiList.Ppi = &Private->UfsHostControllerPpi; + BarAddr = PcdGet32 (PcdUfsPciHostControllerMmioBase); for (Bus = 0; Bus < 256; Bus++) { for (Device = 0; Device < 32; Device++) { for (Function = 0; Function < 8; Function++) { @@ -119,17 +122,57 @@ InitializeUfsHcPeim ( PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE)); PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF); Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET)); + + switch (Size & 0x07) { + case 0x0: + // + // Memory space: anywhere in 32 bit address space + // + MmioSize = (~(Size & 0xFFFFFFF0)) + 1; + break; + case 0x4: + // + // Memory space: anywhere in 64 bit address space + // + MmioSize = Size & 0xFFFFFFF0; + PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF); + Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4)); + + // + // Fix the length to support some specific 64 bit BAR + // + Size |= ((UINT32)(-1) << HighBitSet32 (Size)); + + // + // Calculate the size of 64bit bar + // + MmioSize |= LShiftU64 ((UINT64) Size, 32); + MmioSize = (~(MmioSize)) + 1; + + // + // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR. + // + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0); + break; + default: + // + // Unknown BAR type + // + ASSERT (FALSE); + continue; + }; // // Assign resource to the Ufs Pci host controller's MMIO BAR. // Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register. // - PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs)); + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), BarAddr); PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE)); // // Record the allocated Mmio base address. // - Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs; + Private->UfsHcPciAddr[Private->TotalUfsHcs] = BarAddr; Private->TotalUfsHcs++; + BarAddr += (UINT32)MmioSize; ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS); } } -- 2.39.2