From b66e38b50134728614bbca2a2449a36a5dc2bd91 Mon Sep 17 00:00:00 2001 From: Ming Huang Date: Mon, 29 Oct 2018 12:57:08 +0800 Subject: [PATCH] ArmPkg/ArmGicDxe: Fix GICv3 interrupt routing mode bug Setting GICD_IROUTERn.IRM and GICD_IROUTERn.{Aff3,Aff2,Aff1,Aff0} at the same time is nonsensical (see 8.9.13 in the GICv3 spec, which says of GICD_IROUTERn.IRM that "When this bit is set to 1, GICD_IROUTER.{Aff3,Aff2,Aff1,Aff0} are UNKNOWN"). There is also no guarantee that IRM is implemented (see GICD_TYPER.No1N which indicates whether the implementation supports this or not). Let's thus not set this bit, as we want all SPIs to be delivered to the same CPU, and not be broadcast to all of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Acked-by: Marc Zyngier --- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 01154848f4..1558db3171 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -469,7 +469,7 @@ GicV3DxeInitialize ( for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { MmioWrite32 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), - CpuTarget | ARM_GICD_IROUTER_IRM + CpuTarget ); } } -- 2.39.2