From ba40cb31b69df76a3392219a78cbd7b49ae24c49 Mon Sep 17 00:00:00 2001 From: Michael D Kinney Date: Wed, 16 Aug 2017 16:49:17 -0700 Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support check https://bugzilla.tianocore.org/show_bug.cgi?id=674 Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs. Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Kinney Reviewed-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 6b66c49085..f086b97c30 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,6 +27,7 @@ SMM_CPU_SEMAPHORES mSmmCpuSemaphores; UINTN mSemaphoreSize; SPIN_LOCK *mPFLock = NULL; SMM_CPU_SYNC_MODE mCpuSmmSyncMode; +BOOLEAN mMachineCheckSupported = FALSE; /** Performs an atomic compare exchange operation to get semaphore. @@ -264,8 +265,12 @@ SmmWaitForApArrival ( ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus); - LmceEn = IsLmceOsEnabled (); - LmceSignal = IsLmceSignaled(); + LmceEn = FALSE; + LmceSignal = FALSE; + if (mMachineCheckSupported) { + LmceEn = IsLmceOsEnabled (); + LmceSignal = IsLmceSignaled(); + } // // Platform implementor should choose a timeout value appropriately: @@ -1366,6 +1371,13 @@ InitializeMpServiceData ( UINTN Index; UINT8 *GdtTssTables; UINTN GdtTableStepSize; + CPUID_VERSION_INFO_EDX RegEdx; + + // + // Determine if this CPU supports machine check + // + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32); + mMachineCheckSupported = (BOOLEAN)(RegEdx.Bits.MCA == 1); // // Allocate memory for all locks and semaphores -- 2.39.2