From bb146ce32dd8edc463e792554351e50b9e5b769f Mon Sep 17 00:00:00 2001
From: "Zeng, Star" <star.zeng@intel.com>
Date: Thu, 21 Oct 2021 11:28:20 +0800
Subject: [PATCH] MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]

This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30].

Signed-off-by: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
 MdePkg/Include/Register/Intel/Cpuid.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
index 6f77e174c1..5ec85ba561 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1587,9 +1587,9 @@ typedef union {
     ///
     UINT32  EnumeratesSupportForCapability:1;
     ///
-    /// [Bit 30] Reserved.
+    /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
     ///
-    UINT32  Reserved3:1;
+    UINT32  EnumeratesSupportForCoreCapabilitiesMsr:1;
     ///
     /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
     /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
-- 
2.39.2