From bcee1b9f172a606b1c4ee86dcda04c15718c4ed9 Mon Sep 17 00:00:00 2001 From: Hao Wu Date: Wed, 15 Feb 2017 16:04:26 +0800 Subject: [PATCH] IntelFspWrapperPkg: Refine casting expression result to bigger size There are cases that the operands of an expression are all with rank less than UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like // UINT8, UINT16, etc. UINT64 c; c = (UINT64) (a + b); Some static code checkers may warn that the expression result might overflow within the rank of "int" (integer promotions) and the result is then cast to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c = (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove the explicit type casts: c = a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with rank less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jiewen Yao --- IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c | 4 ++-- IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c b/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c index 6f06e24cae..089413cc3e 100644 --- a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c +++ b/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded ( // Align buffer on section boundary // ImageContext.ImageAddress += ImageContext.SectionAlignment - 1; - ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)(ImageContext.SectionAlignment - 1)); + ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)ImageContext.SectionAlignment - 1); // // Load the image to our new buffer // diff --git a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c b/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c index 162d244665..accd6e495e 100644 --- a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c +++ b/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c @@ -1,7 +1,7 @@ /** @file Provide FSP API related function. - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -98,7 +98,7 @@ CallFspInit ( EFI_STATUS Status; BOOLEAN InterruptState; - FspInitApi = (FSP_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspInitEntryOffset); + FspInitApi = (FSP_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspInitEntryOffset); InterruptState = SaveAndDisableInterrupts (); Status = Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams); SetInterruptState (InterruptState); @@ -125,7 +125,7 @@ CallFspNotifyPhase ( EFI_STATUS Status; BOOLEAN InterruptState; - NotifyPhaseApi = (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset); + NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset); InterruptState = SaveAndDisableInterrupts (); Status = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams); SetInterruptState (InterruptState); @@ -152,7 +152,7 @@ CallFspMemoryInit ( EFI_STATUS Status; BOOLEAN InterruptState; - FspMemoryInitApi = (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset); + FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset); InterruptState = SaveAndDisableInterrupts (); Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspMemoryInitParams); SetInterruptState (InterruptState); @@ -179,7 +179,7 @@ CallTempRamExit ( EFI_STATUS Status; BOOLEAN InterruptState; - TempRamExitApi = (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset); + TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset); InterruptState = SaveAndDisableInterrupts (); Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam); SetInterruptState (InterruptState); @@ -206,7 +206,7 @@ CallFspSiliconInit ( EFI_STATUS Status; BOOLEAN InterruptState; - FspSiliconInitApi = (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset); + FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset); InterruptState = SaveAndDisableInterrupts (); Status = Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspSiliconInitParam); SetInterruptState (InterruptState); -- 2.39.2