From c45f4c5e759cadb5a95a04cdcc42d09bc83177ca Mon Sep 17 00:00:00 2001 From: Liming Gao Date: Thu, 18 Jan 2018 10:36:13 +0800 Subject: [PATCH] IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass XCODE5 build XCODE5 doesn't support absolute addressing in the assembly code. This change uses lea instruction to get the address. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Jiewen Yao Reviewed-by: Jiewen Yao --- .../Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm index bcc6d70a73..a6ad6cf487 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm @@ -1,5 +1,5 @@ ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -81,7 +81,7 @@ ASM_PFX(AsmExecute32BitCode): ; mov rax, dword 0x10 ; load long mode selector shl rax, 32 - mov r9, ReloadCS ;Assume the ReloadCS is under 4G + lea r9, [ReloadCS] ;Assume the ReloadCS is under 4G or rax, r9 push rax ; @@ -95,7 +95,7 @@ ASM_PFX(AsmExecute32BitCode): ; save the 32-bit function entry and the return address into stack which will be ; retrieve in compatibility mode. ; - mov rax, ReturnBack ;Assume the ReloadCS is under 4G + lea rax, [ReturnBack] ;Assume the ReloadCS is under 4G shl rax, 32 or rax, rcx push rax @@ -110,7 +110,7 @@ ASM_PFX(AsmExecute32BitCode): ; mov rcx, dword 0x8 ; load compatible mode selector shl rcx, 32 - mov rdx, Compatible ; assume address < 4G + lea rdx, [Compatible] ; assume address < 4G or rcx, rdx push rcx retf @@ -208,7 +208,7 @@ ReloadCS: ; pop r9 ; get CS shl r9, 32 ; rcx[32..47] <- Cs - mov rcx, .0 + lea rcx, [.0] or rcx, r9 push rcx retf -- 2.39.2