From ce3e0a906f10a20f5c4ca5111876da0a1b99f52b Mon Sep 17 00:00:00 2001 From: Liming Gao Date: Tue, 14 Jun 2016 15:59:02 +0800 Subject: [PATCH] UefiCpuPkg BaseUefiCpuLib: Convert X64/InitializeFpu.asm to NASM The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/InitializeFpu.asm to X64/InitializeFpu.nasm. And, manually add .rdata section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao --- .../BaseUefiCpuLib/X64/InitializeFpu.nasm | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm new file mode 100644 index 0000000000..904b64e510 --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm @@ -0,0 +1,60 @@ +;------------------------------------------------------------------------------ +;* +;* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+;* This program and the accompanying materials +;* are licensed and made available under the terms and conditions of the BSD License +;* which accompanies this distribution. The full text of the license may be found at +;* http://opensource.org/licenses/bsd-license.php +;* +;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +;* +;* +;------------------------------------------------------------------------------ + + SECTION .rdata +; +; Float control word initial value: +; all exceptions masked, double-extended-precision, round-to-nearest +; +mFpuControlWord: DW 0x37F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +mMmxControlWord: DD 0x1F80 + +DEFAULT REL +SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + ; + ; Initialize floating point units + ; + ; The following opcodes stand for instruction 'finit' + ; to be supported by some 64-bit assemblers + ; + DB 0x9B, 0xDB, 0xE3 + fldcw [mFpuControlWord] + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov rax, cr4 + or rax, BIT9 + mov cr4, rax + + ldmxcsr [mMmxControlWord] + + ret + -- 2.39.2