From d4f167a92a5455c2e90a0a69e281ecb5799678db Mon Sep 17 00:00:00 2001 From: AJFISH Date: Sun, 17 Jan 2010 02:54:31 +0000 Subject: [PATCH] Missed a fix in the Cpu Driver. Added some more debug for Execption handling and clean up some uncached stuff. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9789 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/CpuDxe/Exception.c | 11 +++++++- ArmPkg/Drivers/CpuDxe/Mmu.c | 27 ++++++++++--------- .../DebugUncachedMemoryAllocationLib.c | 2 +- .../UncachedMemoryAllocationLib.c | 4 +-- BeagleBoardPkg/PciEmulation/PciEmulation.c | 7 +---- 5 files changed, 28 insertions(+), 23 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c index f0b682d18d..d46971b33c 100644 --- a/ArmPkg/Drivers/CpuDxe/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/Exception.c @@ -311,7 +311,16 @@ CommonCExceptionHandler ( // you need to subtact out the size of the PE/COFF header to get // get the offset that matches the link map. // - DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader)); + DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader)); + + // If we come from an image it is safe to show the instruction. We know it should not fault + if ((SystemContext.SystemContextArm->CPSR & 0x20) == 0) { + // ARM + DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%08x", *(UINT32 *)(UINTN)SystemContext.SystemContextArm->PC)); + } else { + // Thumb + DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%04x", *(UINT16 *)(UINTN)SystemContext.SystemContextArm->PC)); + } } DEBUG_CODE_END (); DEBUG ((EFI_D_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3)); diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c index 55e049850f..6d512592c2 100644 --- a/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -440,36 +440,37 @@ UpdatePageEntries ( // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) // EntryValue: values at bit positions specified by EntryMask - + EntryMask = ARM_PAGE_DESC_TYPE_MASK; + EntryValue = ARM_PAGE_TYPE_SMALL; // Although the PI spec is unclear on this the GCD guarantees that only // one Attribute bit is set at a time, so we can safely use a switch statement switch (Attributes) { case EFI_MEMORY_UC: // modify cacheability attributes - EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; + EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; // map to strongly ordered - EntryValue = 0; // TEX[2:0] = 0, C=0, B=0 + EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0 break; case EFI_MEMORY_WC: // modify cacheability attributes - EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; + EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; // map to normal non-cachable - EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0 + EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0 break; case EFI_MEMORY_WT: // modify cacheability attributes - EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; + EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; // write through with no-allocate - EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0 + EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0 break; case EFI_MEMORY_WB: // modify cacheability attributes - EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; + EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B; // write back (with allocate) - EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1 + EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1 break; case EFI_MEMORY_WP: @@ -477,8 +478,7 @@ UpdatePageEntries ( case EFI_MEMORY_UCE: // cannot be implemented UEFI definition unclear for ARM // Cause a page fault if these ranges are accessed. - EntryMask = 0x3; - EntryValue = 0; + EntryValue = ARM_PAGE_TYPE_FAULT; DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); break; @@ -861,8 +861,9 @@ CpuReconvertPagesPages ( ) { EFI_STATUS Status; - - // +DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes)); +ASSERT (FALSE); +// // Unmap the alaised Address // Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0); diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c index 80e7c8c472..cdf6a85137 100644 --- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c +++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c @@ -292,7 +292,7 @@ UncachedFreeAlignedPages ( Status = gVirtualUncachedPages->RevertPages (gVirtualUncachedPages, Memory, Pages * EFI_PAGE_SIZE, PcdGet64 (PcdArmUncachedMemoryMask), gAttributes); - Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages); + Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Memory, Pages); ASSERT_EFI_ERROR (Status); } diff --git a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c index 060ba6bf98..830212e4d7 100644 --- a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c +++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c @@ -207,7 +207,7 @@ UncachedInternalAllocateAlignedPages ( } if (AlignedMemory != 0) { - FlushCache(AlignedMemory, EFI_PAGES_TO_SIZE(Pages)); + FlushCache (AlignedMemory, EFI_PAGES_TO_SIZE(Pages)); AlignedMemory = (UINTN)ConvertToUncachedAddress((VOID *)AlignedMemory); } @@ -318,7 +318,7 @@ UncachedInternalAllocateAlignedPool ( *FreePointer = RawAddress; if (AlignedAddress != 0) { - FlushCache(AlignedAddress, AllocationSize); + FlushCache (AlignedAddress, AllocationSize); AlignedAddress = (UINTN)ConvertToUncachedAddress((VOID *)AlignedAddress); } diff --git a/BeagleBoardPkg/PciEmulation/PciEmulation.c b/BeagleBoardPkg/PciEmulation/PciEmulation.c index dee0541971..f558597932 100644 --- a/BeagleBoardPkg/PciEmulation/PciEmulation.c +++ b/BeagleBoardPkg/PciEmulation/PciEmulation.c @@ -318,12 +318,7 @@ PciIoUnmap ( // Make sure we read buffer from uncached memory and not the cache // gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate); - } else if (Map->Operation == EfiPciOperationBusMasterCommonBuffer) { - // - // CPU was using uncached address, so anything in the cached range is bogus - // - gCpu->FlushDataCache (gCpu, Map->DeviceAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate); - } + } FreePool (Map); -- 2.39.2