From e6956d0052a79dd7d45dd633d8201bce8c34bccd Mon Sep 17 00:00:00 2001 From: Abner Chang Date: Fri, 3 Apr 2020 13:51:12 +0800 Subject: [PATCH] .pytool: Add RISC-V architecture on RISC-V EDK2 CI. BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Add RISC-V architecture on RISC-V EDK2 CI testing. Signed-off-by: Abner Chang Reviewed-by: Sean Brogan Cc: Bret Barkelew Cc: Sean Brogan Cc: Leif Lindholm Cc: Michael D Kinney Cc: Gilbert Chen Cc: Daniel Helmut Schaefer --- .pytool/CISettings.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py index 7a8bd33803..79aa12d9f5 100644 --- a/.pytool/CISettings.py +++ b/.pytool/CISettings.py @@ -1,6 +1,7 @@ # @file # # Copyright (c) Microsoft Corporation. +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent ## import os @@ -57,10 +58,12 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag def GetArchitecturesSupported(self): ''' return iterable of edk2 architectures supported by this build ''' - return ("IA32", + return ( + "IA32", "X64", "ARM", - "AARCH64") + "AARCH64", + "RISCV64") def GetTargetsSupported(self): ''' return iterable of edk2 target tags supported by this build ''' @@ -133,6 +136,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag scopes += ("gcc_aarch64_linux",) if "ARM" in self.ActualArchitectures: scopes += ("gcc_arm_linux",) + if "RISCV64" in self.ActualArchitectures: + scopes += ("gcc_riscv64_unknown",) return scopes -- 2.39.2