From f6b139bde7e0a39f83ffad30af58136d5b0738a7 Mon Sep 17 00:00:00 2001 From: Suman Prakash Date: Thu, 20 Apr 2017 18:01:42 +0800 Subject: [PATCH] MdeModulePkg/NvmExpressDxe: Handling return of write to sq and cq db In case of an async command if updating the submission queue tail doorbell fails then the command will not be picked up by device and no completion response will be created. This scenario has to be handled. Also if we create an AsyncRequest element and insert in the async queue, it will never receive a completion so in the timer routine this element won't be freed, resulting in memory leak. Also in case of blocking calls we should capture the status of updating completion queue head doorbell register and return it to caller of PassThru. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Suman Prakash Reviewed-by: Hao Wu --- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c index ef3d772cc2..fb80f39ce8 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c @@ -603,7 +603,7 @@ NvmExpressPassThru ( Private->SqTdbl[QueueId].Sqt ^= 1; } Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]); - PciIo->Mem.Write ( + Status = PciIo->Mem.Write ( PciIo, EfiPciIoWidthUint32, NVME_BAR, @@ -612,6 +612,10 @@ NvmExpressPassThru ( &Data ); + if (EFI_ERROR (Status)) { + goto EXIT; + } + // // For non-blocking requests, return directly if the command is placed // in the submission queue. @@ -695,7 +699,7 @@ NvmExpressPassThru ( } Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]); - PciIo->Mem.Write ( + Status = PciIo->Mem.Write ( PciIo, EfiPciIoWidthUint32, NVME_BAR, -- 2.39.2