From f8113e25001e715390127f23e2197252cbd6d1a2 Mon Sep 17 00:00:00 2001 From: Ray Ni Date: Mon, 8 Apr 2019 15:32:00 +0800 Subject: [PATCH] UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging Reserved6 is changed to Reserved7 because the bit width is changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni Reviewed-by: Eric Dong --- UefiCpuPkg/Include/Register/Cpuid.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h index e0f4f968f4..a67f2a1dff 100644 --- a/UefiCpuPkg/Include/Register/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Cpuid.h @@ -1506,8 +1506,11 @@ typedef union { /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). /// UINT32 AVX512_VPOPCNTDQ:1; - UINT32 Reserved6:2; - + UINT32 Reserved7:1; + /// + /// [Bits 16] Supports 5-level paging if 1. + /// + UINT32 FiveLevelPage:1; /// /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions /// in 64-bit mode. -- 2.39.2