dev_intelliprop.cpp

   1 /*
   2  * dev_intelliprop.cpp
   3  *
   4  * Home page of code is: http://www.smartmontools.org
   5  *
   6  * Copyright (C) 2016 Casey Biemiller  <cbiemiller@intelliprop.com>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #include "config.h"
  12
  13 #include "atacmds.h" //ATTR_PACKED and ASSERT_SIZEOF_STRUCT
  14 #include "dev_interface.h"
  15 #include "dev_intelliprop.h"
  16 #include "dev_tunnelled.h"
  17 #include <errno.h>
  18
  19 const char * dev_intelliprop_cpp_cvsid = "$Id: dev_intelliprop.cpp 4760 2018-08-19 18:45:53Z chrfranke $"
  20   DEV_INTELLIPROP_H_CVSID;
  21
  22 //Vendor Specific log addresses
  23 #define LOG_C0           0xc0
  24
  25 // VS LOG MODE CONTROL BITS
  26 enum {
  27   IPROP_VS_LOG_MODE_CTL_AUTO_SUPPORTED   = (0 << 0), // NOTE: Not supported
  28   IPROP_VS_LOG_MODE_CTL_MANUAL_SUPPORTED = (1 << 1),
  29   IPROP_VS_LOG_MODE_CTL_AUTO_ENABLED     = (0 << 2), // NOTE: Not supported
  30   IPROP_VS_LOG_MODE_CTL_MANUAL_ENABLED   = (1 << 3),
  31 };
  32
  33 // VS LOG PORT SETTING BITS
  34 enum {
  35   IPROP_VS_LOG_PORT_WRITE_ENABLE_MASK  = 0xC000,
  36   IPROP_VS_LOG_PORT_WRITE_ENABLE_VALID = 0x8000,
  37   IPROP_VS_LOG_PORT_RX_DC_GAIN_MASK    = 0x3000,
  38   IPROP_VS_LOG_PORT_RX_DC_GAIN_SHIFT   = 12,
  39   IPROP_VS_LOG_PORT_RX_EQ_MASK         = 0x0F00,
  40   IPROP_VS_LOG_PORT_RX_EQ_SHIFT        = 8,
  41   IPROP_VS_LOG_PORT_TX_PREEMP_MASK     = 0x00F8,
  42   IPROP_VS_LOG_PORT_TX_PREEMP_SHIFT    = 3,
  43   IPROP_VS_LOG_PORT_TX_VOD_MASK        = 0x0007,
  44   IPROP_VS_LOG_PORT_TX_VOD_SHIFT       = 0,
  45 };
  46
  47 //This struct is used for the Vendor Specific log C0 on devices that support it.
  48 #pragma pack(1)
  49 struct iprop_internal_log
  50 {
  51   uint32_t drive_select;       // Bytes - [  3:  0] of Log C0
  52   uint32_t obsolete;           // Bytes - [  7:  4] of Log C0
  53   uint8_t  mode_control;       // Byte  - [      8] of Log C0
  54   uint8_t  log_passthrough;    // Byte  - [      9] of Log C0
  55   uint16_t tier_id;            // Bytes - [ 11: 10] of Log C0
  56   uint32_t hw_version;         // Bytes - [ 15: 12] of Log C0
  57   uint32_t fw_version;         // Bytes - [ 19: 16] of Log C0
  58   uint8_t  variant[8];         // Bytes - [ 27: 20] of Log C0
  59   uint8_t  reserved[228];      // Bytes - [255: 28] of Log C0
  60   uint16_t port_0_settings[3]; // Bytes - [263:256] of Log C0
  61   uint16_t port_0_reserved;
  62   uint16_t port_1_settings[3]; // Bytes - [271:264] of Log C0
  63   uint16_t port_1_reserved;
  64   uint16_t port_2_settings[3]; // Bytes - [279:272] of Log C0
  65   uint16_t port_2_reserved;
  66   uint16_t port_3_settings[3]; // Bytes - [287:280] of Log C0
  67   uint16_t port_3_reserved;
  68   uint16_t port_4_settings[3]; // Bytes - [295:288] of Log C0
  69   uint16_t port_4_reserved;
  70   uint8_t  reserved2[214];     // Bytes - [509:296] of Log C0
  71   uint16_t crc;                // Bytes - [511:510] of Log C0
  72 } ATTR_PACKED;
  73 #pragma pack()
  74 ASSERT_SIZEOF_STRUCT(iprop_internal_log, 512);
  75
  76 /**
  77  * buffer is a pointer to a buffer of bytes, which should include data and
  78  *   also CRC if the function is being used to check CRC
  79  * len is the number of bytes in the buffer (including CRC if it is present)
  80  * check_crc is a boolean value, set true to check an existing CRC, false
  81  *   to calculate a new CRC
  82  */
  83 static uint16_t iprop_crc16_1(uint8_t * buffer, uint32_t len, bool check_crc)
  84 {
  85   uint8_t crc[16];
  86   uint16_t crc_final = 0;
  87   uint8_t crc_msb;
  88   uint8_t data_msb;
  89   uint32_t total_len;
  90
  91   // Initialize CRC array
  92   for (uint32_t ii = 0; ii < 16; ii++) {
  93     crc[ii] = 0;
  94     //crc[ii] = (crc_in >> ii) & 1;
  95   }
  96
  97   // If calculating a new CRC, we need to pad the data with extra zeroes
  98   total_len = check_crc ? len : len + 2;
  99
 100   // Loop for each byte, plus extra for the CRC itself
 101   for (uint32_t ii = 0; ii < total_len; ii++) {
 102     uint8_t data = (ii < len) ? buffer[ii] : 0;
 103
 104     // Loop for each bit
 105     for (uint32_t jj = 0; jj < 8; jj++) {
 106       crc_msb = crc[15];
 107       data_msb = (data >> (8 - jj - 1)) & 1;
 108
 109       crc[15] = crc[14] ^ crc_msb;
 110       crc[14] = crc[13];
 111       crc[13] = crc[12];
 112       crc[12] = crc[11];
 113       crc[11] = crc[10] ^ crc_msb;
 114       crc[10] = crc[9];
 115       crc[9] = crc[8] ^ crc_msb;
 116       crc[8] = crc[7] ^ crc_msb;
 117       crc[7] = crc[6] ^ crc_msb;
 118       crc[6] = crc[5];
 119       crc[5] = crc[4] ^ crc_msb;
 120       crc[4] = crc[3] ^ crc_msb;
 121       crc[3] = crc[2];
 122       crc[2] = crc[1] ^ crc_msb;
 123       crc[1] = crc[0] ^ crc_msb;
 124       crc[0] = data_msb ^ crc_msb;
 125     }
 126   }
 127
 128   // Convert CRC array to final value
 129   for (uint32_t ii = 0; ii < 16; ii++) {
 130     if (crc[ii] == 1) {
 131       crc_final |= (1 << ii);
 132     } else {
 133       crc_final &= ~(1 << ii);
 134     }
 135   }
 136
 137   return crc_final;
 138 }
 139
 140 static void iprop_dump_log_structure(struct iprop_internal_log const * const log)
 141 {
 142   pout("Dumping LOG Structure:\n");
 143   pout("  drive_select:           0x%08x\n", log->drive_select);
 144   pout("  obsolete:               0x%08x\n", log->obsolete);
 145   pout("  mode_control:           0x%02x\n", log->mode_control);
 146   pout("  log_passthrough:        0x%02x\n", log->log_passthrough);
 147   pout("  tier_id:                0x%04x\n", log->tier_id);
 148   pout("  hw_version:             0x%08x\n", log->hw_version);
 149   pout("  fw_version:             0x%08x\n", log->fw_version);
 150   pout("  variant:                \"");
 151   for (int ii = 0; ii < 8; ii++) {
 152     pout("%c", (char)log->variant[ii]);
 153   }
 154   pout("\"\n");
 155   pout("  port_0_settings(Gen 1): 0x%08x\n", log->port_0_settings[0]);
 156   pout("  port_0_settings(Gen 2): 0x%08x\n", log->port_0_settings[1]);
 157   pout("  port_0_settings(Gen 3): 0x%08x\n", log->port_0_settings[2]);
 158   pout("  port_1_settings(Gen 1): 0x%08x\n", log->port_1_settings[0]);
 159   pout("  port_1_settings(Gen 2): 0x%08x\n", log->port_1_settings[1]);
 160   pout("  port_1_settings(Gen 3): 0x%08x\n", log->port_1_settings[2]);
 161   pout("  port_2_settings(Gen 1): 0x%08x\n", log->port_2_settings[0]);
 162   pout("  port_2_settings(Gen 2): 0x%08x\n", log->port_2_settings[1]);
 163   pout("  port_2_settings(Gen 3): 0x%08x\n", log->port_2_settings[2]);
 164   pout("  port_3_settings(Gen 1): 0x%08x\n", log->port_3_settings[0]);
 165   pout("  port_3_settings(Gen 2): 0x%08x\n", log->port_3_settings[1]);
 166   pout("  port_3_settings(Gen 3): 0x%08x\n", log->port_3_settings[2]);
 167   pout("  port_4_settings(Gen 1): 0x%08x\n", log->port_4_settings[0]);
 168   pout("  port_4_settings(Gen 2): 0x%08x\n", log->port_4_settings[1]);
 169   pout("  port_4_settings(Gen 3): 0x%08x\n", log->port_4_settings[2]);
 170   pout("  crc:                    0x%04x\n", log->crc);
 171   pout("\n");
 172 }
 173
 174 static bool iprop_switch_routed_drive(ata_device * device, int drive_select)
 175 {
 176   // Declare a log page buffer and initialize it with what is on the drive currently
 177   iprop_internal_log write_payload;
 178   if (!ataReadLogExt(device, LOG_C0, 0, 0, &write_payload, 1))
 179     return device->set_err(EIO, "intelliprop: Initial Read Log failed: %s", device->get_errmsg());
 180
 181   // Check the returned data is good
 182   uint16_t const crc_check = iprop_crc16_1((uint8_t *)&write_payload,
 183                                            sizeof(struct iprop_internal_log),
 184                                            false);
 185
 186
 187    //If this first read fails the crc check, the log can be still sent with routing information
 188    //as long as everything else in the log is zeroed. So there is no need to return false.
 189   if (crc_check != 0) {
 190     if (ata_debugmode)
 191       pout("Intelliprop WARNING: Received log crc(0x%04X) is invalid!\n", crc_check);
 192     iprop_dump_log_structure(&write_payload);
 193     memset(&write_payload, 0, sizeof(struct iprop_internal_log));
 194   }
 195
 196   //The option to read the log, even if successful, could be useful
 197   if (ata_debugmode)
 198     iprop_dump_log_structure(&write_payload);
 199
 200   // Modify the current drive select to what we were given
 201   write_payload.drive_select = (uint32_t)drive_select;
 202   if (ata_debugmode)
 203     pout("Intelliprop - Change to port 0x%08X.\n", write_payload.drive_select);
 204   write_payload.log_passthrough = 0; // TEST (Set to 1, non hydra member drive will abort --> test error handling)
 205   write_payload.tier_id = 0; // TEST (Set to non-zero, non hydra member drive will abort --> test error handling)
 206
 207   // Update the CRC area
 208   uint16_t const crc_new = iprop_crc16_1((uint8_t *)&write_payload,
 209                                          sizeof(struct iprop_internal_log) - sizeof(uint16_t),
 210                                          false);
 211   write_payload.crc = (crc_new >> 8) | (crc_new << 8);
 212
 213   // Check our CRC work
 214   uint16_t const crc_check2 = iprop_crc16_1((uint8_t *)&write_payload,
 215                                             sizeof(struct iprop_internal_log),
 216                                             false);
 217   if (crc_check2 != 0)
 218     return device->set_err(EIO, "intelliprop: Re-calculated log crc(0x%04X) is invalid!", crc_check2);
 219
 220   // Apply the Write LOG
 221   if (!ataWriteLogExt(device, LOG_C0, 0, &write_payload, 1))
 222     return device->set_err(EIO, "intelliprop: Write Log failed: %s", device->get_errmsg());
 223
 224   // Check that the Write LOG was applied
 225   iprop_internal_log check_payload;
 226   if (!ataReadLogExt(device, LOG_C0, 0, 0, &check_payload, 1))
 227     return device->set_err(EIO, "intelliprop: Secondary Read Log failed: %s", device->get_errmsg());
 228
 229   if (check_payload.drive_select != write_payload.drive_select) {
 230     if (ata_debugmode > 1)
 231       iprop_dump_log_structure(&check_payload);
 232     return device->set_err(EIO, "intelliprop: Current drive select val(0x%08X) is not expected(0x%08X)",
 233          check_payload.drive_select,
 234          write_payload.drive_select);
 235   }
 236
 237   return true;
 238 }
 239
 240 namespace intelliprop {
 241
 242 class intelliprop_device
 243 : public tunnelled_device<
 244     /*implements*/ ata_device,
 245     /*by using an*/ ata_device
 246   >
 247 {
 248 public:
 249   intelliprop_device(smart_interface * intf, unsigned phydrive, ata_device * atadev);
 250
 251   virtual ~intelliprop_device() throw();
 252
 253   virtual bool open();
 254
 255   virtual bool ata_pass_through(const ata_cmd_in & in, ata_cmd_out & out);
 256
 257 private:
 258   unsigned m_phydrive;
 259 };
 260
 261
 262 intelliprop_device::intelliprop_device(smart_interface * intf, unsigned phydrive, ata_device * atadev)
 263 : smart_device(intf, atadev->get_dev_name(), "intelliprop", "intelliprop"),
 264   tunnelled_device<ata_device, ata_device>(atadev),
 265   m_phydrive(phydrive)
 266 {
 267   set_info().info_name = strprintf("%s [intelliprop_disk_%u]", atadev->get_info_name(), phydrive);
 268 }
 269
 270 intelliprop_device::~intelliprop_device() throw()
 271 {
 272 }
 273
 274 bool intelliprop_device::open()
 275 {
 276   if (!tunnelled_device<ata_device, ata_device>::open())
 277     return false;
 278
 279   ata_device * atadev = get_tunnel_dev();
 280   if (!iprop_switch_routed_drive(atadev, m_phydrive)) {
 281     close();
 282     return set_err(atadev->get_err());
 283   }
 284
 285   return true;
 286 }
 287
 288 bool intelliprop_device::ata_pass_through(const ata_cmd_in & in, ata_cmd_out & out)
 289 {
 290   return get_tunnel_dev()->ata_pass_through(in, out);
 291 }
 292 }//namespace
 293
 294 ata_device * get_intelliprop_device(smart_interface * intf, unsigned phydrive, ata_device * atadev)
 295 {
 296   return new intelliprop::intelliprop_device(intf, phydrive, atadev);
 297 }