/* >= 0 values are CPU number */
/* H_GET_CPU_CHARACTERISTICS return values */
-#define H_GET_CPU_CHAR_CHAR_ORI31_SPEC_BAR PPC_BIT(0)
-#define H_GET_CPU_CHAR_CHAR_BCCTR_SERIAL PPC_BIT(1)
-#define H_GET_CPU_CHAR_CHAR_ORI30_L1_FLUSH PPC_BIT(2)
-#define H_GET_CPU_CHAR_CHAR_MTTRIG2_L1_FLUSH PPC_BIT(3)
-#define H_GET_CPU_CHAR_CHAR_L1D_PRIVATE PPC_BIT(4)
-#define H_GET_CPU_CHAR_CHAR_BC_HINTS_HONORED PPC_BIT(5)
-#define H_GET_CPU_CHAR_CHAR_MTTRID01_THR_CFG PPC_BIT(6)
-
-#define H_GET_CPU_CHAR_BEHAV_FAV_SEC_VS_PERF PPC_BIT(0)
-#define H_GET_CPU_CHAR_BEHAV_L1_FLUSH_LOW_PRIV PPC_BIT(1)
-#define H_GET_CPU_CHAR_BEHAV_SPEC_BAR_BNDS_CHK PPC_BIT(2)
+#define H_CPU_CHAR_SPEC_BAR_ORI31 (1ull << 63) // IBM bit 0
+#define H_CPU_CHAR_BCCTRL_SERIALISED (1ull << 62) // IBM bit 1
+#define H_CPU_CHAR_L1D_FLUSH_ORI30 (1ull << 61) // IBM bit 2
+#define H_CPU_CHAR_L1D_FLUSH_TRIG2 (1ull << 60) // IBM bit 3
+#define H_CPU_CHAR_L1D_THREAD_PRIV (1ull << 59) // IBM bit 4
+
+#define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
+#define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
+#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ull << 61) // IBM bit 2
/* Flag values used in H_REGISTER_PROC_TBL hcall */
#define PROC_TABLE_OP_MASK 0x18
if (rc == H_SUCCESS) {
types = L1D_FLUSH_NONE;
- if (character & H_GET_CPU_CHAR_CHAR_MTTRIG2_L1_FLUSH)
+ if (character & H_CPU_CHAR_L1D_FLUSH_TRIG2)
types |= L1D_FLUSH_MTTRIG;
- if (character & H_GET_CPU_CHAR_CHAR_ORI30_L1_FLUSH)
+ if (character & H_CPU_CHAR_L1D_FLUSH_ORI30)
types |= L1D_FLUSH_ORI;
/* Use fallback if nothing set in hcall */
if (types == L1D_FLUSH_NONE)
types = L1D_FLUSH_FALLBACK;
- if (!(behaviour & H_GET_CPU_CHAR_BEHAV_L1_FLUSH_LOW_PRIV))
+ if (!(behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
enable = false;
} else {
/* Default to fallback if case hcall is not available */