KVM: arm64: vgic-v3: Add misc Group-0 handlers

BugLink: https://bugs.launchpad.net/bugs/1673564
A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Acked-by: Christoffer Dall <cdall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(backported from commit eab0b2dc4f6f34147e3d10da49ab8032e15dbea0)
[ dannf: Drop the SYS_ prefix and move the system register macro
  definitions from asm/sysreg.h to asm/arch_gicv3.h for consistency
  with code prior to 0e9884fe ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 1b2b331016f8b93e52bb60655ddc48c839c32cb2..52e97cd88689e02e0d8186872bb78ec5f67be2a4 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -20,7 +20,11 @@
 
 #include <asm/sysreg.h>
 
+#define ICC_IAR0_EL1                   sys_reg(3, 0, 12, 8, 0)
+#define ICC_EOIR0_EL1                  sys_reg(3, 0, 12, 8, 1)
+#define ICC_HPPIR0_EL1                 sys_reg(3, 0, 12, 8, 2)
 #define ICC_BPR0_EL1                   sys_reg(3, 0, 12, 8, 3)
+#define ICC_AP0Rn_EL1(n)               sys_reg(3, 0, 12, 8, 4 | n)
 #define ICC_AP1Rn_EL1(n)               sys_reg(3, 0, 12, 9, n)
 #define ICC_EOIR1_EL1                  sys_reg(3, 0, 12, 12, 1)
 #define ICC_DIR_EL1                    sys_reg(3, 0, 12, 11, 1)

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index feda602176930a524d56899eef5d300023b2894b..86824e99ecb8d4aeae4af4107096fd6591e64900 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -931,9 +931,11 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
 
        switch (sysreg) {
+       case ICC_IAR0_EL1:
        case ICC_IAR1_EL1:
                fn = __vgic_v3_read_iar;
                break;
+       case ICC_EOIR0_EL1:
        case ICC_EOIR1_EL1:
                fn = __vgic_v3_write_eoir;
                break;
@@ -949,30 +951,35 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                else
                        fn = __vgic_v3_write_bpr1;
                break;
+       case ICC_AP0Rn_EL1(0):
        case ICC_AP1Rn_EL1(0):
                if (is_read)
                        fn = __vgic_v3_read_apxr0;
                else
                        fn = __vgic_v3_write_apxr0;
                break;
+       case ICC_AP0Rn_EL1(1):
        case ICC_AP1Rn_EL1(1):
                if (is_read)
                        fn = __vgic_v3_read_apxr1;
                else
                        fn = __vgic_v3_write_apxr1;
                break;
+       case ICC_AP0Rn_EL1(2):
        case ICC_AP1Rn_EL1(2):
                if (is_read)
                        fn = __vgic_v3_read_apxr2;
                else
                        fn = __vgic_v3_write_apxr2;
                break;
+       case ICC_AP0Rn_EL1(3):
        case ICC_AP1Rn_EL1(3):
                if (is_read)
                        fn = __vgic_v3_read_apxr3;
                else
                        fn = __vgic_v3_write_apxr3;
                break;
+       case ICC_HPPIR0_EL1:
        case ICC_HPPIR1_EL1:
                fn = __vgic_v3_read_hppir;
                break;