KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler

BugLink: https://bugs.launchpad.net/bugs/1673564
Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1
register, which is located in the ICH_VMCR_EL2.VENG0 field.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(backported from commit fbc48a0011deb3d51cb657ca9c0f9083f41c0665)
[ dannf: Drop the SYS_ prefix and move the ICV_IGNREN0_EL1 macro definition
  from asm/sysreg.h to asm/arch_gicv3.h for consistency with code
  prior to 0e9884fe ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index ba64f86bbeab640113d7bf66fa6cf0e3b321b760..1b2b331016f8b93e52bb60655ddc48c839c32cb2 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -29,6 +29,7 @@
 #define ICC_PMR_EL1                    sys_reg(3, 0, 4, 6, 0)
 #define ICC_CTLR_EL1                   sys_reg(3, 0, 12, 12, 4)
 #define ICC_SRE_EL1                    sys_reg(3, 0, 12, 12, 5)
+#define ICC_GRPEN0_EL1                 sys_reg(3, 0, 12, 12, 6)
 #define ICC_GRPEN1_EL1                 sys_reg(3, 0, 12, 12, 7)
 #define ICC_BPR1_EL1                   sys_reg(3, 0, 12, 12, 3)
 #define ICC_HPPIR1_EL1                 sys_reg(3, 0, 12, 12, 2)

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 8e51d9b4f5e911188358dae9522d2ea7aa2b06aa..feda602176930a524d56899eef5d300023b2894b 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -738,11 +738,28 @@ static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int
        __vgic_v3_clear_active_lr(lr, lr_val);
 }
 
+static void __hyp_text __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
+}
+
 static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
 }
 
+static void __hyp_text __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & 1)
+               vmcr |= ICH_VMCR_ENG0_MASK;
+       else
+               vmcr &= ~ICH_VMCR_ENG0_MASK;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u64 val = vcpu_get_reg(vcpu, rt);
@@ -959,6 +976,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        case ICC_HPPIR1_EL1:
                fn = __vgic_v3_read_hppir;
                break;
+       case ICC_GRPEN0_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_igrpen0;
+               else
+                       fn = __vgic_v3_write_igrpen0;
+               break;
        case ICC_BPR0_EL1:
                if (is_read)
                        fn = __vgic_v3_read_bpr0;