arm64: Add workaround for Cavium Thunder erratum 30115

BugLink: https://bugs.launchpad.net/bugs/1673564
Some Cavium Thunder CPUs suffer a problem where a KVM guest may
inadvertently cause the host kernel to quit receiving interrupts.

Use the Group-0/1 trapping in order to deal with it.

[maz]: Adapted patch to the Group-0/1 trapping, reworked commit log

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(cherry picked from commit 690a341577f9adf2c275ababe0dcefe91898bbf0)
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 10f2dddbf449475ae5bdc79945330d09cf5f6683..f5f93dca54b72594ee34dddcac52ce7fb7b385e4 100644 (file)
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -62,6 +62,7 @@ stable kernels.
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A                         |
+| Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |
 |                |                 |                 |                             |
 | Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |
 |                |                 |                 |                             |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ea5ec59537de2a8ffbc3fc06cb83829784a59c90..c2f43f62a9fc4e534b0162133b7a5cf8b3485c57 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -486,6 +486,17 @@ config CAVIUM_ERRATUM_27456
 
          If unsure, say Y.
 
+config CAVIUM_ERRATUM_30115
+       bool "Cavium erratum 30115: Guest may disable interrupts in host"
+       default y
+       help
+         On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
+         1.2, and T83 Pass 1.0, KVM guest execution may disable
+         interrupts in host. Trapping both GICv3 group-0 and group-1
+         accesses sidesteps the issue.
+
+         If unsure, say Y.
+
 config QCOM_FALKOR_ERRATUM_1003
        bool "Falkor E1003: Incorrect translation due to ASID change"
        default y

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index b3aab8a17868e04eb9ba8ea46cb51cf3f1b1f2f8..8d2272c6822c703b2076eccc04667ecb775c6860 100644 (file)
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -38,7 +38,8 @@
 #define ARM64_WORKAROUND_REPEAT_TLBI           17
 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003     18
 #define ARM64_WORKAROUND_858921                        19
+#define ARM64_WORKAROUND_CAVIUM_30115          20
 
-#define ARM64_NCAPS                            20
+#define ARM64_NCAPS                            21
 
 #endif /* __ASM_CPUCAPS_H */

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 2ed2a7657711c54df5e9f698868d936d309a8830..0e27f86ee70976b82cce63ce0b475eb94c2c606b 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -132,6 +132,27 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                .capability = ARM64_WORKAROUND_CAVIUM_27456,
                MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
        },
+#endif
+#ifdef CONFIG_CAVIUM_ERRATUM_30115
+       {
+       /* Cavium ThunderX, T88 pass 1.x - 2.2 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX, 0x00,
+                          (1 << MIDR_VARIANT_SHIFT) | 2),
+       },
+       {
+       /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
+       },
+       {
+       /* Cavium ThunderX, T83 pass 1.0 */
+               .desc = "Cavium erratum 30115",
+               .capability = ARM64_WORKAROUND_CAVIUM_30115,
+               MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
+       },
 #endif
        {
                .desc = "Mismatched cache line size",

diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index f0ace9792270dd45d60e35419504674d3043b440..41ff3775018f8a8604037c8f4515db523daec354 100644 (file)
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -376,6 +376,13 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
        if (kvm_vgic_global_state.vcpu_base == 0)
                kvm_info("disabling GICv2 emulation\n");
 
+#ifdef CONFIG_ARM64
+       if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
+               group0_trap = true;
+               group1_trap = true;
+       }
+#endif
+
        if (group0_trap || group1_trap) {
                kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");
                static_branch_enable(&vgic_v3_cpuif_trap);