KVM: arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

BugLink: https://bugs.launchpad.net/bugs/1673564
Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP1Rn_EL2 registers.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
(backported from commit f9e7449c780f688bf61a13dfa8c344afeb4ad6e0)
[ dannf: Drop the SYS_ prefix and move the ICV_AP1Rn_EL1 macro definition
  from asm/sysreg.h to asm/arch_gicv3.h for consistency with code
  prior to 0e9884fe ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f37e3a21f6e767cb16d473b46ebe7ca487a47fb4..7bf1d46272bc7faaf73ff56d8997babee91b9506 100644 (file)
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -20,6 +20,7 @@
 
 #include <asm/sysreg.h>
 
+#define ICC_AP1Rn_EL1(n)               sys_reg(3, 0, 12, 9, n)
 #define ICC_EOIR1_EL1                  sys_reg(3, 0, 12, 12, 1)
 #define ICC_DIR_EL1                    sys_reg(3, 0, 12, 11, 1)
 #define ICC_IAR1_EL1                   sys_reg(3, 0, 12, 12, 0)

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 1af7f94a525592a12b88421d157bf21b8389d891..2fc92c1d01ae0c04aa638facf354b669a783a645 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -769,6 +769,76 @@ static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int
        __vgic_v3_write_vmcr(vmcr);
 }
 
+static void __hyp_text __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
+{
+       u32 val;
+
+       if (!__vgic_v3_get_group(vcpu))
+               val = __vgic_v3_read_ap0rn(n);
+       else
+               val = __vgic_v3_read_ap1rn(n);
+
+       vcpu_set_reg(vcpu, rt, val);
+}
+
+static void __hyp_text __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
+{
+       u32 val = vcpu_get_reg(vcpu, rt);
+
+       if (!__vgic_v3_get_group(vcpu))
+               __vgic_v3_write_ap0rn(val, n);
+       else
+               __vgic_v3_write_ap1rn(val, n);
+}
+
+static void __hyp_text __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 0);
+}
+
+static void __hyp_text __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 1);
+}
+
+static void __hyp_text __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 2);
+}
+
+static void __hyp_text __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 3);
+}
+
+static void __hyp_text __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 0);
+}
+
+static void __hyp_text __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 1);
+}
+
+static void __hyp_text __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 2);
+}
+
+static void __hyp_text __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 3);
+}
+
 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
 {
        int rt;
@@ -809,6 +879,30 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                else
                        fn = __vgic_v3_write_bpr1;
                break;
+       case ICC_AP1Rn_EL1(0):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr0;
+               else
+                       fn = __vgic_v3_write_apxr0;
+               break;
+       case ICC_AP1Rn_EL1(1):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr1;
+               else
+                       fn = __vgic_v3_write_apxr1;
+               break;
+       case ICC_AP1Rn_EL1(2):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr2;
+               else
+                       fn = __vgic_v3_write_apxr2;
+               break;
+       case ICC_AP1Rn_EL1(3):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr3;
+               else
+                       fn = __vgic_v3_write_apxr3;
+               break;
        default:
                return 0;
        }