powerpc/mm/radix: Improve _tlbiel_pid to be usable for PWC flushes

BugLink: http://bugs.launchpad.net/bugs/1709220
The PWC flush only needs a single set call, just like the
full (RIC=2) flush.

This will allow us to get rid of the dedicated _tlbiel_pwc()

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(cherry picked from commit 5ce5fe14ed0302315061cf97ce67accd1b25b938 linux-next)
Signed-off-by: Joseph Salisbury <joseph.salisbury@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Seth Forshee <seth.forshee@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 5e531e46ca3af30e6b0b3e209c4015f8baea77e1..f1af3ab5200f7b7c61898d2a3c74aa779019d2ef 100644 (file)
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -53,12 +53,15 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
         */
        __tlbiel_pid(pid, 0, ric);
 
-       if (ric == RIC_FLUSH_ALL)
-               /* For the remaining sets, just flush the TLB */
-               ric = RIC_FLUSH_TLB;
+       /* For PWC, only one flush is needed */
+       if (ric == RIC_FLUSH_PWC) {
+               asm volatile("ptesync": : :"memory");
+               return;
+       }
 
+       /* For the remaining sets, just flush the TLB */
        for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
-               __tlbiel_pid(pid, set, ric);
+               __tlbiel_pid(pid, set, RIC_FLUSH_TLB);
 
        asm volatile("ptesync": : :"memory");
        asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");