]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/commitdiff
powerpc/perf: Avoid spurious PMU interrupts after idle
authorNicholas Piggin <npiggin@gmail.com>
Wed, 9 Aug 2017 13:44:00 +0000 (15:44 +0200)
committerKleber Sacilotto de Souza <kleber.souza@canonical.com>
Wed, 23 Aug 2017 15:48:08 +0000 (17:48 +0200)
BugLink: http://bugs.launchpad.net/bugs/1709352
POWER9 DD2 can see spurious PMU interrupts after state-loss idle in
some conditions.

A solution is to save and reload MMCR0 over state-loss idle.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Acked-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Tested-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(cherry picked from commit 101dd590a7fa37954540cf3149a1c502c0acc524)
Signed-off-by: Rodrigo R. Galvao <rosattig@linux.vnet.ibm.com>
Acked-by: Seth Forshee <seth.forshee@canonical.com>
Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
arch/powerpc/kernel/idle_book3s.S

index fb762ee5ac6f719249770461c81c93ed8a38c868..e003fb99085d9e4e4a22a9a3a7fd0de0020a27de 100644 (file)
@@ -29,6 +29,7 @@
  * Use unused space in the interrupt stack to save and restore
  * registers for winkle support.
  */
+#define _MMCR0 GPR0
 #define _SDR1  GPR3
 #define _RPR   GPR4
 #define _SPURR GPR5
@@ -282,6 +283,14 @@ power_enter_stop:
        b       pnv_wakeup_noloss
 
 .Lhandle_esl_ec_set:
+       /*
+        * POWER9 DD2 can incorrectly set PMAO when waking up after a
+        * state-loss idle. Saving and restoring MMCR0 over idle is a
+        * workaround.
+        */
+       mfspr   r4,SPRN_MMCR0
+       std     r4,_MMCR0(r1)
+
 /*
  * Check if the requested state is a deep idle state.
  */
@@ -434,10 +443,14 @@ FTR_SECTION_ELSE_NESTED(70)
 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
        /*
         * Workaround for POWER9, if we lost resources, the ERAT
-        * might have been mixed up and needs flushing.
+        * might have been mixed up and needs flushing. We also need
+        * to reload MMCR0 (see comment above).
         */
        blt     cr3,1f
        PPC_INVALIDATE_ERAT
+       ld      r1,PACAR1(r13)
+       ld      r4,_MMCR0(r1)
+       mtspr   SPRN_MMCR0,r4
 1:
        /*
         * POWER ISA 3. Use PSSCR to determine if we