patches/kernel/0003-pci-Enable-overrides-for-missing-ACS-capabilities-4..patch

   1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
   2 From: Mark Weiman <mark.weiman@markzz.com>
   3 Date: Wed, 7 Feb 2018 16:04:03 -0500
   4 Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.15)
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This an updated version of Alex Williamson's patch from:
  10 https://lkml.org/lkml/2013/5/30/513
  11
  12 Original commit message follows:
  13 PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that
  14 allows us to control whether transactions are allowed to be redirected
  15 in various subnodes of a PCIe topology.  For instance, if two
  16 endpoints are below a root port or downsteam switch port, the
  17 downstream port may optionally redirect transactions between the
  18 devices, bypassing upstream devices.  The same can happen internally
  19 on multifunction devices.  The transaction may never be visible to the
  20 upstream devices.
  21
  22 One upstream device that we particularly care about is the IOMMU.  If
  23 a redirection occurs in the topology below the IOMMU, then the IOMMU
  24 cannot provide isolation between devices.  This is why the PCIe spec
  25 encourages topologies to include ACS support.  Without it, we have to
  26 assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation.
  27
  28 Unfortunately, far too many topologies do not support ACS to make this
  29 a steadfast requirement.  Even the latest chipsets from Intel are only
  30 sporadically supporting ACS.  We have trouble getting interconnect
  31 vendors to include the PCIe spec required PCIe capability, let alone
  32 suggested features.
  33
  34 Therefore, we need to add some flexibility.  The pcie_acs_override=
  35 boot option lets users opt-in specific devices or sets of devices to
  36 assume ACS support.  The "downstream" option assumes full ACS support
  37 on root ports and downstream switch ports.  The "multifunction"
  38 option assumes the subset of ACS features available on multifunction
  39 endpoints and upstream switch ports are supported.  The "id:nnnn:nnnn"
  40 option enables ACS support on devices matching the provided vendor
  41 and device IDs, allowing more strategic ACS overrides.  These options
  42 may be combined in any order.  A maximum of 16 id specific overrides
  43 are available.  It's suggested to use the most limited set of options
  44 necessary to avoid completely disabling ACS across the topology.
  45 Note to hardware vendors, we have facilities to permanently quirk
  46 specific devices which enforce isolation but not provide an ACS
  47 capability.  Please contact me to have your devices added and save
  48 your customers the hassle of this boot option.
  49
  50 Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
  51 ---
  52  .../admin-guide/kernel-parameters.txt         |   9 ++
  53  drivers/pci/quirks.c                          | 101 ++++++++++++++++++
  54  2 files changed, 110 insertions(+)
  55
  56 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
  57 index 51210d10d905..ceb1b471d249 100644
  58 --- a/Documentation/admin-guide/kernel-parameters.txt
  59 +++ b/Documentation/admin-guide/kernel-parameters.txt
  60 @@ -3049,6 +3049,15 @@
  61                 nomsi           [MSI] If the PCI_MSI kernel config parameter is
  62                                 enabled, this kernel boot option can be used to
  63                                 disable the use of MSI interrupts system-wide.
  64 +               pci_acs_override =
  65 +                                       [PCIE] Override missing PCIe ACS support for:
  66 +                               downstream
  67 +                                       All downstream ports - full ACS capabilities
  68 +                               multifunction
  69 +                                       Add multifunction devices - multifunction ACS subset
  70 +                               id:nnnn:nnnn
  71 +                                       Specific device - full ACS capabilities
  72 +                                       Specified as vid:did (vendor/device ID) in hex
  73                 noioapicquirk   [APIC] Disable all boot interrupt quirks.
  74                                 Safety option to keep boot IRQs enabled. This
  75                                 should never be necessary.
  76 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
  77 index facd0d08a380..6ed8f3ead0dd 100644
  78 --- a/drivers/pci/quirks.c
  79 +++ b/drivers/pci/quirks.c
  80 @@ -3703,6 +3703,106 @@ static int __init pci_apply_final_quirks(void)
  81
  82  fs_initcall_sync(pci_apply_final_quirks);
  83
  84 +static bool acs_on_downstream;
  85 +static bool acs_on_multifunction;
  86 +
  87 +#define NUM_ACS_IDS 16
  88 +struct acs_on_id {
  89 +       unsigned short vendor;
  90 +       unsigned short device;
  91 +};
  92 +static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
  93 +static u8 max_acs_id;
  94 +
  95 +static __init int pcie_acs_override_setup(char *p)
  96 +{
  97 +       if (!p)
  98 +               return -EINVAL;
  99 +
 100 +       while (*p) {
 101 +               if (!strncmp(p, "downstream", 10))
 102 +                       acs_on_downstream = true;
 103 +               if (!strncmp(p, "multifunction", 13))
 104 +                       acs_on_multifunction = true;
 105 +               if (!strncmp(p, "id:", 3)) {
 106 +                       char opt[5];
 107 +                       int ret;
 108 +                       long val;
 109 +
 110 +                       if (max_acs_id >= NUM_ACS_IDS - 1) {
 111 +                               pr_warn("Out of PCIe ACS override slots (%d)\n",
 112 +                                               NUM_ACS_IDS);
 113 +                               goto next;
 114 +                       }
 115 +
 116 +                       p += 3;
 117 +                       snprintf(opt, 5, "%s", p);
 118 +                       ret = kstrtol(opt, 16, &val);
 119 +                       if (ret) {
 120 +                               pr_warn("PCIe ACS ID parse error %d\n", ret);
 121 +                               goto next;
 122 +                       }
 123 +                       acs_on_ids[max_acs_id].vendor = val;
 124 +                       p += strcspn(p, ":");
 125 +                       if (*p != ':') {
 126 +                               pr_warn("PCIe ACS invalid ID\n");
 127 +                               goto next;
 128 +                       }
 129 +
 130 +                       p++;
 131 +                       snprintf(opt, 5, "%s", p);
 132 +                       ret = kstrtol(opt, 16, &val);
 133 +                       if (ret) {
 134 +                               pr_warn("PCIe ACS ID parse error %d\n", ret);
 135 +                               goto next;
 136 +                       }
 137 +                       acs_on_ids[max_acs_id].device = val;
 138 +                       max_acs_id++;
 139 +               }
 140 +next:
 141 +               p += strcspn(p, ",");
 142 +               if (*p == ',')
 143 +                       p++;
 144 +       }
 145 +
 146 +       if (acs_on_downstream || acs_on_multifunction || max_acs_id)
 147 +               pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
 148 +
 149 +       return 0;
 150 +}
 151 +early_param("pcie_acs_override", pcie_acs_override_setup);
 152 +
 153 +static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
 154 +{
 155 +       int i;
 156 +
 157 +       /* Never override ACS for legacy devices or devices with ACS caps */
 158 +       if (!pci_is_pcie(dev) ||
 159 +               pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
 160 +                       return -ENOTTY;
 161 +
 162 +       for (i = 0; i < max_acs_id; i++)
 163 +               if (acs_on_ids[i].vendor == dev->vendor &&
 164 +                       acs_on_ids[i].device == dev->device)
 165 +                               return 1;
 166 +
 167 +       switch (pci_pcie_type(dev)) {
 168 +               case PCI_EXP_TYPE_DOWNSTREAM:
 169 +               case PCI_EXP_TYPE_ROOT_PORT:
 170 +                       if (acs_on_downstream)
 171 +                               return 1;
 172 +                       break;
 173 +               case PCI_EXP_TYPE_ENDPOINT:
 174 +               case PCI_EXP_TYPE_UPSTREAM:
 175 +               case PCI_EXP_TYPE_LEG_END:
 176 +               case PCI_EXP_TYPE_RC_END:
 177 +                       if (acs_on_multifunction && dev->multifunction)
 178 +                               return 1;
 179 +       }
 180 +
 181 +       return -ENOTTY;
 182 +}
 183 +
 184  /*
 185   * Following are device-specific reset methods which can be used to
 186   * reset a single function if other methods (e.g. FLR, PM D0->D3) are
 187 @@ -4542,6 +4642,7 @@ static const struct pci_dev_acs_enabled {
 188         { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
 189         /* APM X-Gene */
 190         { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
 191 +       { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
 192         { 0 }
 193  };
 194