projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7a25ec8e MP |
1 | What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr |
| 2 | Date: November 2014 | |
| 3 | KernelVersion: 3.19 | |
| 4 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 5 | Description: (RW) Disables write access to the Trace RAM by stopping the | |
| 6 | formatter after a defined number of words have been stored | |
| 7 | following the trigger event. Additional interface for this | |
| 8 | driver are expected to be added as it matures. | |
| 7d83d177 MP |
9 | |
| 10 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz | |
| 11 | Date: March 2016 | |
| 12 | KernelVersion: 4.7 | |
| 13 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 14 | Description: (R) Defines the size, in 32-bit words, of the local RAM buffer. | |
| 15 | The value is read directly from HW register RSZ, 0x004. | |
| 16 | ||
| 17 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts | |
| 18 | Date: March 2016 | |
| 19 | KernelVersion: 4.7 | |
| 20 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 21 | Description: (R) Shows the value held by the TMC status register. The value | |
| 22 | is read directly from HW register STS, 0x00C. | |
| 23 | ||
| 24 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp | |
| 25 | Date: March 2016 | |
| 26 | KernelVersion: 4.7 | |
| 27 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 28 | Description: (R) Shows the value held by the TMC RAM Read Pointer register | |
| 29 | that is used to read entries from the Trace RAM over the APB | |
| 30 | interface. The value is read directly from HW register RRP, | |
| 31 | 0x014. | |
| 32 | ||
| 33 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp | |
| 34 | Date: March 2016 | |
| 35 | KernelVersion: 4.7 | |
| 36 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 37 | Description: (R) Shows the value held by the TMC RAM Write Pointer register | |
| 38 | that is used to sets the write pointer to write entries from | |
| 39 | the CoreSight bus into the Trace RAM. The value is read directly | |
| 40 | from HW register RWP, 0x018. | |
| 41 | ||
| 42 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg | |
| 43 | Date: March 2016 | |
| 44 | KernelVersion: 4.7 | |
| 45 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 46 | Description: (R) Similar to "trigger_cntr" above except that this value is | |
| 47 | read directly from HW register TRG, 0x01C. | |
| 48 | ||
| 49 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl | |
| 50 | Date: March 2016 | |
| 51 | KernelVersion: 4.7 | |
| 52 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 53 | Description: (R) Shows the value held by the TMC Control register. The value | |
| 54 | is read directly from HW register CTL, 0x020. | |
| 55 | ||
| 56 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr | |
| 57 | Date: March 2016 | |
| 58 | KernelVersion: 4.7 | |
| 59 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 60 | Description: (R) Shows the value held by the TMC Formatter and Flush Status | |
| 61 | register. The value is read directly from HW register FFSR, | |
| 62 | 0x300. | |
| 63 | ||
| 64 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr | |
| 65 | Date: March 2016 | |
| 66 | KernelVersion: 4.7 | |
| 67 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 68 | Description: (R) Shows the value held by the TMC Formatter and Flush Control | |
| 69 | register. The value is read directly from HW register FFCR, | |
| 70 | 0x304. | |
| 71 | ||
| 72 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode | |
| 73 | Date: March 2016 | |
| 74 | KernelVersion: 4.7 | |
| 75 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 76 | Description: (R) Shows the value held by the TMC Mode register, which | |
| 77 | indicate the mode the device has been configured to enact. The | |
| 78 | The value is read directly from the MODE register, 0x028. | |
| 79 | ||
| 80 | What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid | |
| 81 | Date: March 2016 | |
| 82 | KernelVersion: 4.7 | |
| 83 | Contact: Mathieu Poirier <mathieu.poirier@linaro.org> | |
| 84 | Description: (R) Indicates the capabilities of the Coresight TMC. | |
| 85 | The value is read directly from the DEVID register, 0xFC8, |