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da0df92b CE |
1 | /* |
2 | edid.S: EDID data template | |
3 | ||
4 | Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org> | |
5 | ||
6 | This program is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU General Public License | |
8 | as published by the Free Software Foundation; either version 2 | |
9 | of the License, or (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | ||
22 | /* Manufacturer */ | |
23 | #define MFG_LNX1 'L' | |
24 | #define MFG_LNX2 'N' | |
25 | #define MFG_LNX3 'X' | |
26 | #define SERIAL 0 | |
27 | #define YEAR 2012 | |
28 | #define WEEK 5 | |
29 | ||
30 | /* EDID 1.3 standard definitions */ | |
31 | #define XY_RATIO_16_10 0b00 | |
32 | #define XY_RATIO_4_3 0b01 | |
33 | #define XY_RATIO_5_4 0b10 | |
34 | #define XY_RATIO_16_9 0b11 | |
35 | ||
4cbe1bfa DT |
36 | /* Provide defaults for the timing bits */ |
37 | #ifndef ESTABLISHED_TIMING1_BITS | |
38 | #define ESTABLISHED_TIMING1_BITS 0x00 | |
39 | #endif | |
40 | #ifndef ESTABLISHED_TIMING2_BITS | |
41 | #define ESTABLISHED_TIMING2_BITS 0x00 | |
42 | #endif | |
43 | #ifndef ESTABLISHED_TIMING3_BITS | |
44 | #define ESTABLISHED_TIMING3_BITS 0x00 | |
45 | #endif | |
46 | ||
da0df92b CE |
47 | #define mfgname2id(v1,v2,v3) \ |
48 | ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f)) | |
49 | #define swap16(v1) ((v1>>8)+((v1&0xff)<<8)) | |
50 | #define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f)) | |
51 | #define msbs4(v1,v2,v3,v4) \ | |
52 | (((v1&0x03)>>2)+((v2&0x03)>>4)+((v3&0x03)>>6)+((v4&0x03)>>8)) | |
53 | #define pixdpi2mm(pix,dpi) ((pix*25)/dpi) | |
54 | #define xsize pixdpi2mm(XPIX,DPI) | |
55 | #define ysize pixdpi2mm(YPIX,DPI) | |
56 | ||
57 | .data | |
58 | ||
59 | /* Fixed header pattern */ | |
60 | header: .byte 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00 | |
61 | ||
62 | mfg_id: .word swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3)) | |
63 | ||
64 | prod_code: .word 0 | |
65 | ||
66 | /* Serial number. 32 bits, little endian. */ | |
67 | serial_number: .long SERIAL | |
68 | ||
69 | /* Week of manufacture */ | |
70 | week: .byte WEEK | |
71 | ||
72 | /* Year of manufacture, less 1990. (1990-2245) | |
73 | If week=255, it is the model year instead */ | |
74 | year: .byte YEAR-1990 | |
75 | ||
76 | version: .byte VERSION /* EDID version, usually 1 (for 1.3) */ | |
77 | revision: .byte REVISION /* EDID revision, usually 3 (for 1.3) */ | |
78 | ||
79 | /* If Bit 7=1 Digital input. If set, the following bit definitions apply: | |
80 | Bits 6-1 Reserved, must be 0 | |
81 | Bit 0 Signal is compatible with VESA DFP 1.x TMDS CRGB, | |
82 | 1 pixel per clock, up to 8 bits per color, MSB aligned, | |
83 | If Bit 7=0 Analog input. If clear, the following bit definitions apply: | |
84 | Bits 6-5 Video white and sync levels, relative to blank | |
85 | 00=+0.7/-0.3 V; 01=+0.714/-0.286 V; | |
86 | 10=+1.0/-0.4 V; 11=+0.7/0 V | |
87 | Bit 4 Blank-to-black setup (pedestal) expected | |
88 | Bit 3 Separate sync supported | |
89 | Bit 2 Composite sync (on HSync) supported | |
90 | Bit 1 Sync on green supported | |
91 | Bit 0 VSync pulse must be serrated when somposite or | |
92 | sync-on-green is used. */ | |
93 | video_parms: .byte 0x6d | |
94 | ||
95 | /* Maximum horizontal image size, in centimetres | |
96 | (max 292 cm/115 in at 16:9 aspect ratio) */ | |
97 | max_hor_size: .byte xsize/10 | |
98 | ||
99 | /* Maximum vertical image size, in centimetres. | |
100 | If either byte is 0, undefined (e.g. projector) */ | |
101 | max_vert_size: .byte ysize/10 | |
102 | ||
103 | /* Display gamma, minus 1, times 100 (range 1.00-3.5 */ | |
104 | gamma: .byte 120 | |
105 | ||
106 | /* Bit 7 DPMS standby supported | |
107 | Bit 6 DPMS suspend supported | |
108 | Bit 5 DPMS active-off supported | |
109 | Bits 4-3 Display type: 00=monochrome; 01=RGB colour; | |
110 | 10=non-RGB multicolour; 11=undefined | |
111 | Bit 2 Standard sRGB colour space. Bytes 25-34 must contain | |
112 | sRGB standard values. | |
113 | Bit 1 Preferred timing mode specified in descriptor block 1. | |
114 | Bit 0 GTF supported with default parameter values. */ | |
115 | dsp_features: .byte 0xea | |
116 | ||
117 | /* Chromaticity coordinates. */ | |
118 | /* Red and green least-significant bits | |
119 | Bits 7-6 Red x value least-significant 2 bits | |
120 | Bits 5-4 Red y value least-significant 2 bits | |
121 | Bits 3-2 Green x value lst-significant 2 bits | |
122 | Bits 1-0 Green y value least-significant 2 bits */ | |
123 | red_green_lsb: .byte 0x5e | |
124 | ||
125 | /* Blue and white least-significant 2 bits */ | |
126 | blue_white_lsb: .byte 0xc0 | |
127 | ||
128 | /* Red x value most significant 8 bits. | |
129 | 0-255 encodes 0-0.996 (255/256); 0-0.999 (1023/1024) with lsbits */ | |
130 | red_x_msb: .byte 0xa4 | |
131 | ||
132 | /* Red y value most significant 8 bits */ | |
133 | red_y_msb: .byte 0x59 | |
134 | ||
135 | /* Green x and y value most significant 8 bits */ | |
136 | green_x_y_msb: .byte 0x4a,0x98 | |
137 | ||
138 | /* Blue x and y value most significant 8 bits */ | |
139 | blue_x_y_msb: .byte 0x25,0x20 | |
140 | ||
141 | /* Default white point x and y value most significant 8 bits */ | |
142 | white_x_y_msb: .byte 0x50,0x54 | |
143 | ||
144 | /* Established timings */ | |
145 | /* Bit 7 720x400 @ 70 Hz | |
146 | Bit 6 720x400 @ 88 Hz | |
147 | Bit 5 640x480 @ 60 Hz | |
148 | Bit 4 640x480 @ 67 Hz | |
149 | Bit 3 640x480 @ 72 Hz | |
150 | Bit 2 640x480 @ 75 Hz | |
151 | Bit 1 800x600 @ 56 Hz | |
152 | Bit 0 800x600 @ 60 Hz */ | |
4cbe1bfa | 153 | estbl_timing1: .byte ESTABLISHED_TIMING1_BITS |
da0df92b CE |
154 | |
155 | /* Bit 7 800x600 @ 72 Hz | |
156 | Bit 6 800x600 @ 75 Hz | |
157 | Bit 5 832x624 @ 75 Hz | |
158 | Bit 4 1024x768 @ 87 Hz, interlaced (1024x768) | |
159 | Bit 3 1024x768 @ 60 Hz | |
160 | Bit 2 1024x768 @ 72 Hz | |
161 | Bit 1 1024x768 @ 75 Hz | |
162 | Bit 0 1280x1024 @ 75 Hz */ | |
4cbe1bfa | 163 | estbl_timing2: .byte ESTABLISHED_TIMING2_BITS |
da0df92b CE |
164 | |
165 | /* Bit 7 1152x870 @ 75 Hz (Apple Macintosh II) | |
166 | Bits 6-0 Other manufacturer-specific display mod */ | |
4cbe1bfa | 167 | estbl_timing3: .byte ESTABLISHED_TIMING3_BITS |
da0df92b CE |
168 | |
169 | /* Standard timing */ | |
170 | /* X resolution, less 31, divided by 8 (256-2288 pixels) */ | |
171 | std_xres: .byte (XPIX/8)-31 | |
172 | /* Y resolution, X:Y pixel ratio | |
173 | Bits 7-6 X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9. | |
174 | Bits 5-0 Vertical frequency, less 60 (60-123 Hz) */ | |
175 | std_vres: .byte (XY_RATIO<<6)+VFREQ-60 | |
176 | .fill 7,2,0x0101 /* Unused */ | |
177 | ||
178 | descriptor1: | |
179 | /* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */ | |
180 | clock: .word CLOCK/10 | |
181 | ||
182 | /* Horizontal active pixels 8 lsbits (0-4095) */ | |
183 | x_act_lsb: .byte XPIX&0xff | |
184 | /* Horizontal blanking pixels 8 lsbits (0-4095) | |
185 | End of active to start of next active. */ | |
186 | x_blk_lsb: .byte XBLANK&0xff | |
187 | /* Bits 7-4 Horizontal active pixels 4 msbits | |
188 | Bits 3-0 Horizontal blanking pixels 4 msbits */ | |
189 | x_msbs: .byte msbs2(XPIX,XBLANK) | |
190 | ||
191 | /* Vertical active lines 8 lsbits (0-4095) */ | |
192 | y_act_lsb: .byte YPIX&0xff | |
193 | /* Vertical blanking lines 8 lsbits (0-4095) */ | |
194 | y_blk_lsb: .byte YBLANK&0xff | |
195 | /* Bits 7-4 Vertical active lines 4 msbits | |
196 | Bits 3-0 Vertical blanking lines 4 msbits */ | |
197 | y_msbs: .byte msbs2(YPIX,YBLANK) | |
198 | ||
199 | /* Horizontal sync offset pixels 8 lsbits (0-1023) From blanking start */ | |
200 | x_snc_off_lsb: .byte XOFFSET&0xff | |
201 | /* Horizontal sync pulse width pixels 8 lsbits (0-1023) */ | |
202 | x_snc_pls_lsb: .byte XPULSE&0xff | |
203 | /* Bits 7-4 Vertical sync offset lines 4 lsbits -63) | |
204 | Bits 3-0 Vertical sync pulse width lines 4 lsbits -63) */ | |
205 | y_snc_lsb: .byte ((YOFFSET-63)<<4)+(YPULSE-63) | |
206 | /* Bits 7-6 Horizontal sync offset pixels 2 msbits | |
207 | Bits 5-4 Horizontal sync pulse width pixels 2 msbits | |
208 | Bits 3-2 Vertical sync offset lines 2 msbits | |
209 | Bits 1-0 Vertical sync pulse width lines 2 msbits */ | |
210 | xy_snc_msbs: .byte msbs4(XOFFSET,XPULSE,YOFFSET,YPULSE) | |
211 | ||
212 | /* Horizontal display size, mm, 8 lsbits (0-4095 mm, 161 in) */ | |
213 | x_dsp_size: .byte xsize&0xff | |
214 | ||
215 | /* Vertical display size, mm, 8 lsbits (0-4095 mm, 161 in) */ | |
216 | y_dsp_size: .byte ysize&0xff | |
217 | ||
218 | /* Bits 7-4 Horizontal display size, mm, 4 msbits | |
219 | Bits 3-0 Vertical display size, mm, 4 msbits */ | |
220 | dsp_size_mbsb: .byte msbs2(xsize,ysize) | |
221 | ||
222 | /* Horizontal border pixels (each side; total is twice this) */ | |
223 | x_border: .byte 0 | |
224 | /* Vertical border lines (each side; total is twice this) */ | |
225 | y_border: .byte 0 | |
226 | ||
227 | /* Bit 7 Interlaced | |
228 | Bits 6-5 Stereo mode: 00=No stereo; other values depend on bit 0: | |
229 | Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar, | |
230 | sync=1 during left; 11=4-way interleaved stereo | |
231 | Bit 0=1 2-way interleaved stereo: 01=Right image on even lines; | |
232 | 10=Left image on even lines; 11=side-by-side | |
233 | Bits 4-3 Sync type: 00=Analog composite; 01=Bipolar analog composite; | |
234 | 10=Digital composite (on HSync); 11=Digital separate | |
235 | Bit 2 If digital separate: Vertical sync polarity (1=positive) | |
236 | Other types: VSync serrated (HSync during VSync) | |
237 | Bit 1 If analog sync: Sync on all 3 RGB lines (else green only) | |
238 | Digital: HSync polarity (1=positive) | |
239 | Bit 0 2-way line-interleaved stereo, if bits 4-3 are not 00. */ | |
240 | features: .byte 0x18+(VSYNC_POL<<2)+(HSYNC_POL<<1) | |
241 | ||
242 | descriptor2: .byte 0,0 /* Not a detailed timing descriptor */ | |
243 | .byte 0 /* Must be zero */ | |
244 | .byte 0xff /* Descriptor is monitor serial number (text) */ | |
245 | .byte 0 /* Must be zero */ | |
246 | start1: .ascii "Linux #0" | |
247 | end1: .byte 0x0a /* End marker */ | |
248 | .fill 12-(end1-start1), 1, 0x20 /* Padded spaces */ | |
249 | descriptor3: .byte 0,0 /* Not a detailed timing descriptor */ | |
250 | .byte 0 /* Must be zero */ | |
251 | .byte 0xfd /* Descriptor is monitor range limits */ | |
252 | .byte 0 /* Must be zero */ | |
253 | start2: .byte VFREQ-1 /* Minimum vertical field rate (1-255 Hz) */ | |
254 | .byte VFREQ+1 /* Maximum vertical field rate (1-255 Hz) */ | |
255 | .byte (CLOCK/(XPIX+XBLANK))-1 /* Minimum horizontal line rate | |
256 | (1-255 kHz) */ | |
257 | .byte (CLOCK/(XPIX+XBLANK))+1 /* Maximum horizontal line rate | |
258 | (1-255 kHz) */ | |
259 | .byte (CLOCK/10000)+1 /* Maximum pixel clock rate, rounded up | |
260 | to 10 MHz multiple (10-2550 MHz) */ | |
261 | .byte 0 /* No extended timing information type */ | |
262 | end2: .byte 0x0a /* End marker */ | |
263 | .fill 12-(end2-start2), 1, 0x20 /* Padded spaces */ | |
264 | descriptor4: .byte 0,0 /* Not a detailed timing descriptor */ | |
265 | .byte 0 /* Must be zero */ | |
266 | .byte 0xfc /* Descriptor is text */ | |
267 | .byte 0 /* Must be zero */ | |
268 | start3: .ascii TIMING_NAME | |
269 | end3: .byte 0x0a /* End marker */ | |
270 | .fill 12-(end3-start3), 1, 0x20 /* Padded spaces */ | |
271 | extensions: .byte 0 /* Number of extensions to follow */ | |
272 | checksum: .byte CRC /* Sum of all bytes must be 0 */ |