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1 | The MSI Driver Guide HOWTO |
2 | Tom L Nguyen tom.l.nguyen@intel.com | |
3 | 10/03/2003 | |
4 | Revised Feb 12, 2004 by Martine Silbermann | |
5 | email: Martine.Silbermann@hp.com | |
6 | Revised Jun 25, 2004 by Tom L Nguyen | |
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7 | Revised Jul 9, 2008 by Matthew Wilcox <willy@linux.intel.com> |
8 | Copyright 2003, 2008 Intel Corporation | |
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9 | |
10 | 1. About this guide | |
11 | ||
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12 | This guide describes the basics of Message Signaled Interrupts (MSIs), |
13 | the advantages of using MSI over traditional interrupt mechanisms, how | |
14 | to change your driver to use MSI or MSI-X and some basic diagnostics to | |
15 | try if a device doesn't support MSIs. | |
16 | ||
17 | ||
18 | 2. What are MSIs? | |
19 | ||
20 | A Message Signaled Interrupt is a write from the device to a special | |
21 | address which causes an interrupt to be received by the CPU. | |
22 | ||
23 | The MSI capability was first specified in PCI 2.2 and was later enhanced | |
24 | in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X | |
25 | capability was also introduced with PCI 3.0. It supports more interrupts | |
26 | per device than MSI and allows interrupts to be independently configured. | |
27 | ||
28 | Devices may support both MSI and MSI-X, but only one can be enabled at | |
29 | a time. | |
30 | ||
31 | ||
32 | 3. Why use MSIs? | |
33 | ||
34 | There are three reasons why using MSIs can give an advantage over | |
35 | traditional pin-based interrupts. | |
36 | ||
37 | Pin-based PCI interrupts are often shared amongst several devices. | |
38 | To support this, the kernel must call each interrupt handler associated | |
39 | with an interrupt, which leads to reduced performance for the system as | |
40 | a whole. MSIs are never shared, so this problem cannot arise. | |
41 | ||
42 | When a device writes data to memory, then raises a pin-based interrupt, | |
43 | it is possible that the interrupt may arrive before all the data has | |
44 | arrived in memory (this becomes more likely with devices behind PCI-PCI | |
45 | bridges). In order to ensure that all the data has arrived in memory, | |
46 | the interrupt handler must read a register on the device which raised | |
47 | the interrupt. PCI transaction ordering rules require that all the data | |
891f6925 | 48 | arrive in memory before the value may be returned from the register. |
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49 | Using MSIs avoids this problem as the interrupt-generating write cannot |
50 | pass the data writes, so by the time the interrupt is raised, the driver | |
51 | knows that all the data has arrived in memory. | |
52 | ||
53 | PCI devices can only support a single pin-based interrupt per function. | |
54 | Often drivers have to query the device to find out what event has | |
55 | occurred, slowing down interrupt handling for the common case. With | |
56 | MSIs, a device can support more interrupts, allowing each interrupt | |
57 | to be specialised to a different purpose. One possible design gives | |
58 | infrequent conditions (such as errors) their own interrupt which allows | |
59 | the driver to handle the normal interrupt handling path more efficiently. | |
60 | Other possible designs include giving one interrupt to each packet queue | |
61 | in a network card or each port in a storage controller. | |
62 | ||
63 | ||
64 | 4. How to use MSIs | |
65 | ||
66 | PCI devices are initialised to use pin-based interrupts. The device | |
67 | driver has to set up the device to use MSI or MSI-X. Not all machines | |
68 | support MSIs correctly, and for those machines, the APIs described below | |
69 | will simply fail and the device will continue to use pin-based interrupts. | |
70 | ||
71 | 4.1 Include kernel support for MSIs | |
72 | ||
73 | To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI | |
74 | option enabled. This option is only available on some architectures, | |
75 | and it may depend on some other options also being set. For example, | |
76 | on x86, you must also enable X86_UP_APIC or SMP in order to see the | |
77 | CONFIG_PCI_MSI option. | |
78 | ||
79 | 4.2 Using MSI | |
80 | ||
aff17164 CH |
81 | Most of the hard work is done for the driver in the PCI layer. The driver |
82 | simply has to request that the PCI layer set up the MSI capability for this | |
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83 | device. |
84 | ||
aff17164 CH |
85 | To automatically use MSI or MSI-X interrupt vectors, use the following |
86 | function: | |
7918b2dc | 87 | |
aff17164 CH |
88 | int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, |
89 | unsigned int max_vecs, unsigned int flags); | |
7918b2dc | 90 | |
aff17164 CH |
91 | which allocates up to max_vecs interrupt vectors for a PCI device. It |
92 | returns the number of vectors allocated or a negative error. If the device | |
93 | has a requirements for a minimum number of vectors the driver can pass a | |
94 | min_vecs argument set to this limit, and the PCI core will return -ENOSPC | |
95 | if it can't meet the minimum number of vectors. | |
7918b2dc | 96 | |
aff17164 CH |
97 | The flags argument should normally be set to 0, but can be used to pass the |
98 | PCI_IRQ_NOMSI and PCI_IRQ_NOMSIX flag in case a device claims to support | |
99 | MSI or MSI-X, but the support is broken, or to pass PCI_IRQ_NOLEGACY in | |
100 | case the device does not support legacy interrupt lines. | |
1da177e4 | 101 | |
aff17164 CH |
102 | To get the Linux IRQ numbers passed to request_irq() and free_irq() and the |
103 | vectors, use the following function: | |
1da177e4 | 104 | |
aff17164 | 105 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); |
1da177e4 | 106 | |
aff17164 CH |
107 | Any allocated resources should be freed before removing the device using |
108 | the following function: | |
1c8d7b0a | 109 | |
aff17164 | 110 | void pci_free_irq_vectors(struct pci_dev *dev); |
1c8d7b0a | 111 | |
aff17164 CH |
112 | If a device supports both MSI-X and MSI capabilities, this API will use the |
113 | MSI-X facilities in preference to the MSI facilities. MSI-X supports any | |
114 | number of interrupts between 1 and 2048. In contrast, MSI is restricted to | |
115 | a maximum of 32 interrupts (and must be a power of two). In addition, the | |
116 | MSI interrupt vectors must be allocated consecutively, so the system might | |
117 | not be able to allocate as many vectors for MSI as it could for MSI-X. On | |
118 | some platforms, MSI interrupts must all be targeted at the same set of CPUs | |
119 | whereas MSI-X interrupts can all be targeted at different CPUs. | |
1c8d7b0a | 120 | |
aff17164 CH |
121 | If a device supports neither MSI-X or MSI it will fall back to a single |
122 | legacy IRQ vector. | |
1c8d7b0a | 123 | |
aff17164 CH |
124 | The typical usage of MSI or MSI-X interrupts is to allocate as many vectors |
125 | as possible, likely up to the limit supported by the device. If nvec is | |
126 | larger than the number supported by the device it will automatically be | |
127 | capped to the supported limit, so there is no need to query the number of | |
128 | vectors supported beforehand: | |
302a2523 | 129 | |
aff17164 CH |
130 | nvec = pci_alloc_irq_vectors(pdev, 1, nvec, 0); |
131 | if (nvec < 0) | |
132 | goto out_err; | |
302a2523 AG |
133 | |
134 | If a driver is unable or unwilling to deal with a variable number of MSI | |
aff17164 CH |
135 | interrupts it can request a particular number of interrupts by passing that |
136 | number to pci_alloc_irq_vectors() function as both 'min_vecs' and | |
137 | 'max_vecs' parameters: | |
c41ade2e | 138 | |
aff17164 CH |
139 | ret = pci_alloc_irq_vectors(pdev, nvec, nvec, 0); |
140 | if (ret < 0) | |
141 | goto out_err; | |
ff1aa430 | 142 | |
aff17164 CH |
143 | The most notorious example of the request type described above is enabling |
144 | the single MSI mode for a device. It could be done by passing two 1s as | |
145 | 'min_vecs' and 'max_vecs': | |
ff1aa430 | 146 | |
aff17164 CH |
147 | ret = pci_alloc_irq_vectors(pdev, 1, 1, 0); |
148 | if (ret < 0) | |
149 | goto out_err; | |
ff1aa430 | 150 | |
aff17164 CH |
151 | Some devices might not support using legacy line interrupts, in which case |
152 | the PCI_IRQ_NOLEGACY flag can be used to fail the request if the platform | |
153 | can't provide MSI or MSI-X interrupts: | |
ff1aa430 | 154 | |
aff17164 CH |
155 | nvec = pci_alloc_irq_vectors(pdev, 1, nvec, PCI_IRQ_NOLEGACY); |
156 | if (nvec < 0) | |
157 | goto out_err; | |
ff1aa430 | 158 | |
aff17164 | 159 | 4.3 Legacy APIs |
c41ade2e | 160 | |
aff17164 CH |
161 | The following old APIs to enable and disable MSI or MSI-X interrupts should |
162 | not be used in new code: | |
c41ade2e | 163 | |
aff17164 CH |
164 | pci_enable_msi() /* deprecated */ |
165 | pci_enable_msi_range() /* deprecated */ | |
166 | pci_enable_msi_exact() /* deprecated */ | |
167 | pci_disable_msi() /* deprecated */ | |
168 | pci_enable_msix_range() /* deprecated */ | |
169 | pci_enable_msix_exact() /* deprecated */ | |
170 | pci_disable_msix() /* deprecated */ | |
c41ade2e | 171 | |
aff17164 CH |
172 | Additionally there are APIs to provide the number of supported MSI or MSI-X |
173 | vectors: pci_msi_vec_count() and pci_msix_vec_count(). In general these | |
174 | should be avoided in favor of letting pci_alloc_irq_vectors() cap the | |
175 | number of vectors. If you have a legitimate special use case for the count | |
176 | of vectors we might have to revisit that decision and add a | |
177 | pci_nr_irq_vectors() helper that handles MSI and MSI-X transparently. | |
c41ade2e | 178 | |
aff17164 | 179 | 4.4 Considerations when using MSIs |
c41ade2e | 180 | |
aff17164 | 181 | 4.4.1 Spinlocks |
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182 | |
183 | Most device drivers have a per-device spinlock which is taken in the | |
184 | interrupt handler. With pin-based interrupts or a single MSI, it is not | |
185 | necessary to disable interrupts (Linux guarantees the same interrupt will | |
186 | not be re-entered). If a device uses multiple interrupts, the driver | |
187 | must disable interrupts while the lock is held. If the device sends | |
188 | a different interrupt, the driver will deadlock trying to recursively | |
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189 | acquire the spinlock. Such deadlocks can be avoided by using |
190 | spin_lock_irqsave() or spin_lock_irq() which disable local interrupts | |
191 | and acquire the lock (see Documentation/DocBook/kernel-locking). | |
c41ade2e | 192 | |
aff17164 | 193 | 4.5 How to tell whether MSI/MSI-X is enabled on a device |
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194 | |
195 | Using 'lspci -v' (as root) may show some devices with "MSI", "Message | |
196 | Signalled Interrupts" or "MSI-X" capabilities. Each of these capabilities | |
4979de6e | 197 | has an 'Enable' flag which is followed with either "+" (enabled) |
c41ade2e MW |
198 | or "-" (disabled). |
199 | ||
200 | ||
201 | 5. MSI quirks | |
202 | ||
203 | Several PCI chipsets or devices are known not to support MSIs. | |
204 | The PCI stack provides three ways to disable MSIs: | |
205 | ||
206 | 1. globally | |
207 | 2. on all devices behind a specific bridge | |
208 | 3. on a single device | |
209 | ||
210 | 5.1. Disabling MSIs globally | |
211 | ||
212 | Some host chipsets simply don't support MSIs properly. If we're | |
213 | lucky, the manufacturer knows this and has indicated it in the ACPI | |
4979de6e | 214 | FADT table. In this case, Linux automatically disables MSIs. |
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215 | Some boards don't include this information in the table and so we have |
216 | to detect them ourselves. The complete list of these is found near the | |
217 | quirk_disable_all_msi() function in drivers/pci/quirks.c. | |
218 | ||
219 | If you have a board which has problems with MSIs, you can pass pci=nomsi | |
220 | on the kernel command line to disable MSIs on all devices. It would be | |
221 | in your best interests to report the problem to linux-pci@vger.kernel.org | |
222 | including a full 'lspci -v' so we can add the quirks to the kernel. | |
223 | ||
224 | 5.2. Disabling MSIs below a bridge | |
225 | ||
226 | Some PCI bridges are not able to route MSIs between busses properly. | |
227 | In this case, MSIs must be disabled on all devices behind the bridge. | |
228 | ||
229 | Some bridges allow you to enable MSIs by changing some bits in their | |
230 | PCI configuration space (especially the Hypertransport chipsets such | |
231 | as the nVidia nForce and Serverworks HT2000). As with host chipsets, | |
232 | Linux mostly knows about them and automatically enables MSIs if it can. | |
e6b85a1f | 233 | If you have a bridge unknown to Linux, you can enable |
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234 | MSIs in configuration space using whatever method you know works, then |
235 | enable MSIs on that bridge by doing: | |
236 | ||
237 | echo 1 > /sys/bus/pci/devices/$bridge/msi_bus | |
238 | ||
239 | where $bridge is the PCI address of the bridge you've enabled (eg | |
240 | 0000:00:0e.0). | |
241 | ||
242 | To disable MSIs, echo 0 instead of 1. Changing this value should be | |
1b8386f6 | 243 | done with caution as it could break interrupt handling for all devices |
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244 | below this bridge. |
245 | ||
246 | Again, please notify linux-pci@vger.kernel.org of any bridges that need | |
247 | special handling. | |
248 | ||
249 | 5.3. Disabling MSIs on a single device | |
250 | ||
251 | Some devices are known to have faulty MSI implementations. Usually this | |
c2b65e18 | 252 | is handled in the individual device driver, but occasionally it's necessary |
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253 | to handle this with a quirk. Some drivers have an option to disable use |
254 | of MSI. While this is a convenient workaround for the driver author, | |
305af08c | 255 | it is not good practice, and should not be emulated. |
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256 | |
257 | 5.4. Finding why MSIs are disabled on a device | |
258 | ||
259 | From the above three sections, you can see that there are many reasons | |
260 | why MSIs may not be enabled for a given device. Your first step should | |
261 | be to examine your dmesg carefully to determine whether MSIs are enabled | |
262 | for your machine. You should also check your .config to be sure you | |
263 | have enabled CONFIG_PCI_MSI. | |
264 | ||
265 | Then, 'lspci -t' gives the list of bridges above a device. Reading | |
798c794d | 266 | /sys/bus/pci/devices/*/msi_bus will tell you whether MSIs are enabled (1) |
c41ade2e MW |
267 | or disabled (0). If 0 is found in any of the msi_bus files belonging |
268 | to bridges between the PCI root and the device, MSIs are disabled. | |
269 | ||
270 | It is also worth checking the device driver to see whether it supports MSIs. | |
302a2523 AG |
271 | For example, it may contain calls to pci_enable_msi_range() or |
272 | pci_enable_msix_range(). |