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1
2 PCI Error Recovery
3 ------------------
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4 February 2, 2006
5
6 Current document maintainer:
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7 Linas Vepstas <linasvepstas@gmail.com>
8 updated by Richard Lary <rlary@us.ibm.com>
9 and Mike Mason <mmlnx@us.ibm.com> on 27-Jul-2009
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10
11
12Many PCI bus controllers are able to detect a variety of hardware
13PCI errors on the bus, such as parity errors on the data and address
97e4e959 14buses, as well as SERR and PERR errors. Some of the more advanced
c9ab8b68 15chipsets are able to deal with these errors; these include PCI-E chipsets,
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16and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
17pSeries boxes. A typical action taken is to disconnect the affected device,
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18halting all I/O to it. The goal of a disconnection is to avoid system
19corruption; for example, to halt system memory corruption due to DMA's
20to "wild" addresses. Typically, a reconnection mechanism is also
21offered, so that the affected PCI device(s) are reset and put back
22into working condition. The reset phase requires coordination
23between the affected device drivers and the PCI controller chip.
24This document describes a generic API for notifying device drivers
25of a bus disconnection, and then performing error recovery.
26This API is currently implemented in the 2.6.16 and later kernels.
27
28Reporting and recovery is performed in several steps. First, when
29a PCI hardware error has resulted in a bus disconnect, that event
30is reported as soon as possible to all affected device drivers,
31including multiple instances of a device driver on multi-function
32cards. This allows device drivers to avoid deadlocking in spinloops,
33waiting for some i/o-space register to change, when it never will.
34It also gives the drivers a chance to defer incoming I/O as
35needed.
36
37Next, recovery is performed in several stages. Most of the complexity
38is forced by the need to handle multi-function devices, that is,
39devices that have multiple device drivers associated with them.
40In the first stage, each driver is allowed to indicate what type
41of reset it desires, the choices being a simple re-enabling of I/O
fe14acd4 42or requesting a slot reset.
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44If any driver requests a slot reset, that is what will be done.
45
46After a reset and/or a re-enabling of I/O, all drivers are
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47again notified, so that they may then perform any device setup/config
48that may be required. After these have all completed, a final
49"resume normal operations" event is sent out.
50
51The biggest reason for choosing a kernel-based implementation rather
52than a user-space implementation was the need to deal with bus
53disconnects of PCI devices attached to storage media, and, in particular,
54disconnects from devices holding the root file system. If the root
55file system is disconnected, a user-space mechanism would have to go
56through a large number of contortions to complete recovery. Almost all
57of the current Linux file systems are not tolerant of disconnection
58from/reconnection to their underlying block device. By contrast,
59bus errors are easy to manage in the device driver. Indeed, most
60device drivers already handle very similar recovery procedures;
61for example, the SCSI-generic layer already provides significant
62mechanisms for dealing with SCSI bus errors and SCSI bus resets.
63
64
65Detailed Design
66---------------
67Design and implementation details below, based on a chain of
68public email discussions with Ben Herrenschmidt, circa 5 April 2005.
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69
70The error recovery API support is exposed to the driver in the form of
71a structure of function pointers pointed to by a new field in struct
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72pci_driver. A driver that fails to provide the structure is "non-aware",
73and the actual recovery steps taken are platform dependent. The
74arch/powerpc implementation will simulate a PCI hotplug remove/add.
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75
76This structure has the form:
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77struct pci_error_handlers
78{
c9ab8b68 79 int (*error_detected)(struct pci_dev *dev, enum pci_channel_state);
065c6359 80 int (*mmio_enabled)(struct pci_dev *dev);
065c6359 81 int (*slot_reset)(struct pci_dev *dev);
c9ab8b68 82 void (*resume)(struct pci_dev *dev);
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83};
84
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85The possible channel states are:
86enum pci_channel_state {
87 pci_channel_io_normal, /* I/O channel is in normal state */
88 pci_channel_io_frozen, /* I/O to channel is blocked */
89 pci_channel_io_perm_failure, /* PCI card is dead */
90};
91
92Possible return values are:
93enum pci_ers_result {
94 PCI_ERS_RESULT_NONE, /* no result/none/not supported in device driver */
95 PCI_ERS_RESULT_CAN_RECOVER, /* Device driver can recover without slot reset */
96 PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */
97 PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecoverable */
98 PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and operational */
99};
100
101A driver does not have to implement all of these callbacks; however,
102if it implements any, it must implement error_detected(). If a callback
103is not implemented, the corresponding feature is considered unsupported.
104For example, if mmio_enabled() and resume() aren't there, then it
105is assumed that the driver is not doing any direct recovery and requires
2fd260f0 106a slot reset. Typically a driver will want to know about
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107a slot_reset().
108
109The actual steps taken by a platform to recover from a PCI error
110event will be platform-dependent, but will follow the general
111sequence described below.
112
113STEP 0: Error Event
114-------------------
fe14acd4 115A PCI bus error is detected by the PCI hardware. On powerpc, the slot
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116is isolated, in that all I/O is blocked: all reads return 0xffffffff,
117all writes are ignored.
118
119
120STEP 1: Notification
121--------------------
122Platform calls the error_detected() callback on every instance of
123every driver affected by the error.
124
125At this point, the device might not be accessible anymore, depending on
126the platform (the slot will be isolated on powerpc). The driver may
127already have "noticed" the error because of a failing I/O, but this
128is the proper "synchronization point", that is, it gives the driver
129a chance to cleanup, waiting for pending stuff (timers, whatever, etc...)
130to complete; it can take semaphores, schedule, etc... everything but
131touch the device. Within this function and after it returns, the driver
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132shouldn't do any new IOs. Called in task context. This is sort of a
133"quiesce" point. See note about interrupts at the end of this doc.
134
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135All drivers participating in this system must implement this call.
136The driver must return one of the following result codes:
137 - PCI_ERS_RESULT_CAN_RECOVER:
138 Driver returns this if it thinks it might be able to recover
065c6359 139 the HW by just banging IOs or if it wants to be given
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140 a chance to extract some diagnostic information (see
141 mmio_enable, below).
142 - PCI_ERS_RESULT_NEED_RESET:
fe14acd4 143 Driver returns this if it can't recover without a
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144 slot reset.
145 - PCI_ERS_RESULT_DISCONNECT:
146 Driver returns this if it doesn't want to recover at all.
147
148The next step taken will depend on the result codes returned by the
149drivers.
150
151If all drivers on the segment/slot return PCI_ERS_RESULT_CAN_RECOVER,
152then the platform should re-enable IOs on the slot (or do nothing in
153particular, if the platform doesn't isolate slots), and recovery
154proceeds to STEP 2 (MMIO Enable).
155
156If any driver requested a slot reset (by returning PCI_ERS_RESULT_NEED_RESET),
157then recovery proceeds to STEP 4 (Slot Reset).
158
159If the platform is unable to recover the slot, the next step
160is STEP 6 (Permanent Failure).
161
162>>> The current powerpc implementation assumes that a device driver will
163>>> *not* schedule or semaphore in this routine; the current powerpc
065c6359 164>>> implementation uses one kernel thread to notify all devices;
c9ab8b68 165>>> thus, if one device sleeps/schedules, all devices are affected.
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166>>> Doing better requires complex multi-threaded logic in the error
167>>> recovery implementation (e.g. waiting for all notification threads
168>>> to "join" before proceeding with recovery.) This seems excessively
169>>> complex and not worth implementing.
170
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171>>> The current powerpc implementation doesn't much care if the device
172>>> attempts I/O at this point, or not. I/O's will fail, returning
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173>>> a value of 0xff on read, and writes will be dropped. If more than
174>>> EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
175>>> assumes that the device driver has gone into an infinite loop
97e4e959 176>>> and prints an error to syslog. A reboot is then required to
fe14acd4 177>>> get the device working again.
065c6359 178
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179STEP 2: MMIO Enabled
180-------------------
181The platform re-enables MMIO to the device (but typically not the
182DMA), and then calls the mmio_enabled() callback on all affected
183device drivers.
065c6359 184
c9ab8b68 185This is the "early recovery" call. IOs are allowed again, but DMA is
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186not, with some restrictions. This is NOT a callback for the driver to
187start operations again, only to peek/poke at the device, extract diagnostic
188information, if any, and eventually do things like trigger a device local
189reset or some such, but not restart operations. This callback is made if
190all drivers on a segment agree that they can try to recover and if no automatic
191link reset was performed by the HW. If the platform can't just re-enable IOs
192without a slot reset or a link reset, it will not call this callback, and
193instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
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194
195>>> The following is proposed; no platform implements this yet:
196>>> Proposal: All I/O's should be done _synchronously_ from within
197>>> this callback, errors triggered by them will be returned via
198>>> the normal pci_check_whatever() API, no new error_detected()
199>>> callback will be issued due to an error happening here. However,
200>>> such an error might cause IOs to be re-blocked for the whole
201>>> segment, and thus invalidate the recovery that other devices
202>>> on the same segment might have done, forcing the whole segment
203>>> into one of the next states, that is, link reset or slot reset.
204
205The driver should return one of the following result codes:
206 - PCI_ERS_RESULT_RECOVERED
065c6359 207 Driver returns this if it thinks the device is fully
c9ab8b68 208 functional and thinks it is ready to start
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209 normal driver operations again. There is no
210 guarantee that the driver will actually be
211 allowed to proceed, as another driver on the
212 same segment might have failed and thus triggered a
213 slot reset on platforms that support it.
214
c9ab8b68 215 - PCI_ERS_RESULT_NEED_RESET
065c6359 216 Driver returns this if it thinks the device is not
a33f3224 217 recoverable in its current state and it needs a slot
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218 reset to proceed.
219
c9ab8b68 220 - PCI_ERS_RESULT_DISCONNECT
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221 Same as above. Total failure, no recovery even after
222 reset driver dead. (To be defined more precisely)
223
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224The next step taken depends on the results returned by the drivers.
225If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform
226proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
227
228If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
229proceeds to STEP 4 (Slot Reset)
065c6359 230
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231STEP 3: Link Reset
232------------------
2fd260f0 233The platform resets the link. This is a PCI-Express specific step
97e4e959 234and is done whenever a fatal error has been detected that can be
2fd260f0 235"solved" by resetting the link.
c9ab8b68 236
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237STEP 4: Slot Reset
238------------------
c9ab8b68 239
fe14acd4 240In response to a return value of PCI_ERS_RESULT_NEED_RESET, the
97e4e959 241the platform will perform a slot reset on the requesting PCI device(s).
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242The actual steps taken by a platform to perform a slot reset
243will be platform-dependent. Upon completion of slot reset, the
244platform will call the device slot_reset() callback.
245
246Powerpc platforms implement two levels of slot reset:
247soft reset(default) and fundamental(optional) reset.
248
249Powerpc soft reset consists of asserting the adapter #RST line and then
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250restoring the PCI BAR's and PCI configuration header to a state
251that is equivalent to what it would be after a fresh system
252power-on followed by power-on BIOS/system firmware initialization.
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253Soft reset is also known as hot-reset.
254
255Powerpc fundamental reset is supported by PCI Express cards only
256and results in device's state machines, hardware logic, port states and
257configuration registers to initialize to their default conditions.
258
259For most PCI devices, a soft reset will be sufficient for recovery.
260Optional fundamental reset is provided to support a limited number
97e4e959 261of PCI Express devices for which a soft reset is not sufficient
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262for recovery.
263
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264If the platform supports PCI hotplug, then the reset might be
265performed by toggling the slot electrical power off/on.
065c6359 266
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267It is important for the platform to restore the PCI config space
268to the "fresh poweron" state, rather than the "last state". After
269a slot reset, the device driver will almost always use its standard
270device initialization routines, and an unusual config space setup
271may result in hung devices, kernel panics, or silent data corruption.
065c6359 272
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273This call gives drivers the chance to re-initialize the hardware
274(re-download firmware, etc.). At this point, the driver may assume
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275that the card is in a fresh state and is fully functional. The slot
276is unfrozen and the driver has full access to PCI config space,
277memory mapped I/O space and DMA. Interrupts (Legacy, MSI, or MSI-X)
278will also be available.
065c6359 279
fe14acd4 280Drivers should not restart normal I/O processing operations
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281at this point. If all device drivers report success on this
282callback, the platform will call resume() to complete the sequence,
283and let the driver restart normal I/O processing.
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284
285A driver can still return a critical failure for this function if
286it can't get the device operational after reset. If the platform
c9ab8b68 287previously tried a soft reset, it might now try a hard reset (power
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288cycle) and then call slot_reset() again. It the device still can't
289be recovered, there is nothing more that can be done; the platform
290will typically report a "permanent failure" in such a case. The
291device will be considered "dead" in this case.
292
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293Drivers for multi-function cards will need to coordinate among
294themselves as to which driver instance will perform any "one-shot"
295or global device initialization. For example, the Symbios sym53cxx2
296driver performs device init only from PCI function 0:
065c6359 297
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298+ if (PCI_FUNC(pdev->devfn) == 0)
299+ sym_reset_scsi_bus(np, 0);
065c6359 300
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301 Result codes:
302 - PCI_ERS_RESULT_DISCONNECT
303 Same as above.
065c6359 304
fe14acd4 305Drivers for PCI Express cards that require a fundamental reset must
97e4e959 306set the needs_freset bit in the pci_dev structure in their probe function.
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307For example, the QLogic qla2xxx driver sets the needs_freset bit for certain
308PCI card types:
309
310+ /* Set EEH reset type to fundamental if required by hba */
311+ if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
312+ pdev->needs_freset = 1;
313+
314
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315Platform proceeds either to STEP 5 (Resume Operations) or STEP 6 (Permanent
316Failure).
317
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318>>> The current powerpc implementation does not try a power-cycle
319>>> reset if the driver returned PCI_ERS_RESULT_DISCONNECT.
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320>>> However, it probably should.
321
322
323STEP 5: Resume Operations
324-------------------------
325The platform will call the resume() callback on all affected device
326drivers if all drivers on the segment have returned
327PCI_ERS_RESULT_RECOVERED from one of the 3 previous callbacks.
328The goal of this callback is to tell the driver to restart activity,
329that everything is back and running. This callback does not return
330a result code.
331
332At this point, if a new error happens, the platform will restart
333a new error recovery sequence.
334
335STEP 6: Permanent Failure
336-------------------------
337A "permanent failure" has occurred, and the platform cannot recover
338the device. The platform will call error_detected() with a
339pci_channel_state value of pci_channel_io_perm_failure.
340
341The device driver should, at this point, assume the worst. It should
342cancel all pending I/O, refuse all new I/O, returning -EIO to
343higher layers. The device driver should then clean up all of its
344memory and remove itself from kernel operations, much as it would
345during system shutdown.
346
347The platform will typically notify the system operator of the
348permanent failure in some way. If the device is hotplug-capable,
349the operator will probably want to remove and replace the device.
350Note, however, not all failures are truly "permanent". Some are
351caused by over-heating, some by a poorly seated card. Many
352PCI error events are caused by software bugs, e.g. DMA's to
353wild addresses or bogus split transactions due to programming
354errors. See the discussion in powerpc/eeh-pci-error-recovery.txt
355for additional detail on real-life experience of the causes of
356software errors.
357
358
359Conclusion; General Remarks
360---------------------------
fe14acd4 361The way the callbacks are called is platform policy. A platform with
c9ab8b68 362no slot reset capability may want to just "ignore" drivers that can't
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363recover (disconnect them) and try to let other cards on the same segment
364recover. Keep in mind that in most real life cases, though, there will
365be only one driver per segment.
366
c9ab8b68 367Now, a note about interrupts. If you get an interrupt and your
065c6359 368device is dead or has been isolated, there is a problem :)
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369The current policy is to turn this into a platform policy.
370That is, the recovery API only requires that:
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371
372 - There is no guarantee that interrupt delivery can proceed from any
373device on the segment starting from the error detection and until the
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374slot_reset callback is called, at which point interrupts are expected
375to be fully operational.
065c6359 376
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377 - There is no guarantee that interrupt delivery is stopped, that is,
378a driver that gets an interrupt after detecting an error, or that detects
379an error within the interrupt handler such that it prevents proper
065c6359 380ack'ing of the interrupt (and thus removal of the source) should just
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381return IRQ_NOTHANDLED. It's up to the platform to deal with that
382condition, typically by masking the IRQ source during the duration of
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383the error handling. It is expected that the platform "knows" which
384interrupts are routed to error-management capable slots and can deal
c9ab8b68 385with temporarily disabling that IRQ number during error processing (this
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386isn't terribly complex). That means some IRQ latency for other devices
387sharing the interrupt, but there is simply no other way. High end
388platforms aren't supposed to share interrupts between many devices
389anyway :)
390
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391>>> Implementation details for the powerpc platform are discussed in
392>>> the file Documentation/powerpc/eeh-pci-error-recovery.txt
393
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394>>> As of this writing, there is a growing list of device drivers with
395>>> patches implementing error recovery. Not all of these patches are in
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396>>> mainline yet. These may be used as "examples":
397>>>
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398>>> drivers/scsi/ipr
399>>> drivers/scsi/sym53c8xx_2
400>>> drivers/scsi/qla2xxx
401>>> drivers/scsi/lpfc
402>>> drivers/next/bnx2.c
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403>>> drivers/next/e100.c
404>>> drivers/net/e1000
fe14acd4 405>>> drivers/net/e1000e
c9ab8b68 406>>> drivers/net/ixgb
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407>>> drivers/net/ixgbe
408>>> drivers/net/cxgb3
c9ab8b68 409>>> drivers/net/s2io.c
fe14acd4 410>>> drivers/net/qlge
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411
412The End
413-------