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1 | =========================== |
2 | ARM64 CPU Feature Registers | |
3 | =========================== | |
4aa8a472 SP |
4 | |
5 | Author: Suzuki K Poulose <suzuki.poulose@arm.com> | |
6 | ||
7 | ||
8 | This file describes the ABI for exporting the AArch64 CPU ID/feature | |
9 | registers to userspace. The availability of this ABI is advertised | |
10 | via the HWCAP_CPUID in HWCAPs. | |
11 | ||
12 | 1. Motivation | |
b693d0b3 | 13 | ------------- |
4aa8a472 SP |
14 | |
15 | The ARM architecture defines a set of feature registers, which describe | |
16 | the capabilities of the CPU/system. Access to these system registers is | |
17 | restricted from EL0 and there is no reliable way for an application to | |
18 | extract this information to make better decisions at runtime. There is | |
19 | limited information available to the application via HWCAPs, however | |
20 | there are some issues with their usage. | |
21 | ||
22 | a) Any change to the HWCAPs requires an update to userspace (e.g libc) | |
23 | to detect the new changes, which can take a long time to appear in | |
24 | distributions. Exposing the registers allows applications to get the | |
25 | information without requiring updates to the toolchains. | |
26 | ||
27 | b) Access to HWCAPs is sometimes limited (e.g prior to libc, or | |
28 | when ld is initialised at startup time). | |
29 | ||
30 | c) HWCAPs cannot represent non-boolean information effectively. The | |
31 | architecture defines a canonical format for representing features | |
32 | in the ID registers; this is well defined and is capable of | |
33 | representing all valid architecture variations. | |
34 | ||
35 | ||
36 | 2. Requirements | |
b693d0b3 MCC |
37 | --------------- |
38 | ||
39 | a) Safety: | |
4aa8a472 | 40 | |
4aa8a472 SP |
41 | Applications should be able to use the information provided by the |
42 | infrastructure to run safely across the system. This has greater | |
43 | implications on a system with heterogeneous CPUs. | |
44 | The infrastructure exports a value that is safe across all the | |
45 | available CPU on the system. | |
46 | ||
47 | e.g, If at least one CPU doesn't implement CRC32 instructions, while | |
48 | others do, we should report that the CRC32 is not implemented. | |
49 | Otherwise an application could crash when scheduled on the CPU | |
50 | which doesn't support CRC32. | |
51 | ||
b693d0b3 MCC |
52 | b) Security: |
53 | ||
4aa8a472 SP |
54 | Applications should only be able to receive information that is |
55 | relevant to the normal operation in userspace. Hence, some of the | |
56 | fields are masked out(i.e, made invisible) and their values are set to | |
57 | indicate the feature is 'not supported'. See Section 4 for the list | |
58 | of visible features. Also, the kernel may manipulate the fields | |
59 | based on what it supports. e.g, If FP is not supported by the | |
60 | kernel, the values could indicate that the FP is not available | |
61 | (even when the CPU provides it). | |
62 | ||
63 | c) Implementation Defined Features | |
b693d0b3 | 64 | |
4aa8a472 SP |
65 | The infrastructure doesn't expose any register which is |
66 | IMPLEMENTATION DEFINED as per ARMv8-A Architecture. | |
67 | ||
b693d0b3 MCC |
68 | d) CPU Identification: |
69 | ||
4aa8a472 SP |
70 | MIDR_EL1 is exposed to help identify the processor. On a |
71 | heterogeneous system, this could be racy (just like getcpu()). The | |
72 | process could be migrated to another CPU by the time it uses the | |
73 | register value, unless the CPU affinity is set. Hence, there is no | |
74 | guarantee that the value reflects the processor that it is | |
75 | currently executing on. The REVIDR is not exposed due to this | |
76 | constraint, as REVIDR makes sense only in conjunction with the | |
77 | MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs | |
b693d0b3 | 78 | at:: |
4aa8a472 SP |
79 | |
80 | /sys/devices/system/cpu/cpu$ID/regs/identification/ | |
81 | \- midr | |
82 | \- revidr | |
83 | ||
84 | 3. Implementation | |
85 | -------------------- | |
86 | ||
87 | The infrastructure is built on the emulation of the 'MRS' instruction. | |
88 | Accessing a restricted system register from an application generates an | |
89 | exception and ends up in SIGILL being delivered to the process. | |
90 | The infrastructure hooks into the exception handler and emulates the | |
91 | operation if the source belongs to the supported system register space. | |
92 | ||
b693d0b3 MCC |
93 | The infrastructure emulates only the following system register space:: |
94 | ||
4aa8a472 SP |
95 | Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 |
96 | ||
97 | (See Table C5-6 'System instruction encodings for non-Debug System | |
98 | register accesses' in ARMv8 ARM DDI 0487A.h, for the list of | |
99 | registers). | |
100 | ||
101 | The following rules are applied to the value returned by the | |
102 | infrastructure: | |
103 | ||
104 | a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0. | |
105 | b) The value of a reserved field is populated with the reserved | |
106 | value as defined by the architecture. | |
107 | c) The value of a 'visible' field holds the system wide safe value | |
108 | for the particular feature (except for MIDR_EL1, see section 4). | |
109 | d) All other fields (i.e, invisible fields) are set to indicate | |
110 | the feature is missing (as defined by the architecture). | |
111 | ||
112 | 4. List of registers with visible features | |
113 | ------------------------------------------- | |
114 | ||
115 | 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0 | |
b693d0b3 MCC |
116 | |
117 | +------------------------------+---------+---------+ | |
4aa8a472 | 118 | | Name | bits | visible | |
b693d0b3 | 119 | +------------------------------+---------+---------+ |
1a50ec0b RH |
120 | | RNDR | [63-60] | y | |
121 | +------------------------------+---------+---------+ | |
7206dc93 | 122 | | TS | [55-52] | y | |
b693d0b3 | 123 | +------------------------------+---------+---------+ |
3b3b6810 | 124 | | FHM | [51-48] | y | |
b693d0b3 | 125 | +------------------------------+---------+---------+ |
f5e035f8 | 126 | | DP | [47-44] | y | |
b693d0b3 | 127 | +------------------------------+---------+---------+ |
f5e035f8 | 128 | | SM4 | [43-40] | y | |
b693d0b3 | 129 | +------------------------------+---------+---------+ |
f5e035f8 | 130 | | SM3 | [39-36] | y | |
b693d0b3 | 131 | +------------------------------+---------+---------+ |
f5e035f8 | 132 | | SHA3 | [35-32] | y | |
b693d0b3 | 133 | +------------------------------+---------+---------+ |
4aa8a472 | 134 | | RDM | [31-28] | y | |
b693d0b3 | 135 | +------------------------------+---------+---------+ |
4aa8a472 | 136 | | ATOMICS | [23-20] | y | |
b693d0b3 | 137 | +------------------------------+---------+---------+ |
4aa8a472 | 138 | | CRC32 | [19-16] | y | |
b693d0b3 | 139 | +------------------------------+---------+---------+ |
4aa8a472 | 140 | | SHA2 | [15-12] | y | |
b693d0b3 | 141 | +------------------------------+---------+---------+ |
4aa8a472 | 142 | | SHA1 | [11-8] | y | |
b693d0b3 | 143 | +------------------------------+---------+---------+ |
4aa8a472 | 144 | | AES | [7-4] | y | |
b693d0b3 | 145 | +------------------------------+---------+---------+ |
4aa8a472 SP |
146 | |
147 | ||
148 | 2) ID_AA64PFR0_EL1 - Processor Feature Register 0 | |
b693d0b3 MCC |
149 | |
150 | +------------------------------+---------+---------+ | |
4aa8a472 | 151 | | Name | bits | visible | |
b693d0b3 | 152 | +------------------------------+---------+---------+ |
7206dc93 | 153 | | DIT | [51-48] | y | |
b693d0b3 | 154 | +------------------------------+---------+---------+ |
43994d82 | 155 | | SVE | [35-32] | y | |
b693d0b3 | 156 | +------------------------------+---------+---------+ |
4aa8a472 | 157 | | GIC | [27-24] | n | |
b693d0b3 | 158 | +------------------------------+---------+---------+ |
4aa8a472 | 159 | | AdvSIMD | [23-20] | y | |
b693d0b3 | 160 | +------------------------------+---------+---------+ |
4aa8a472 | 161 | | FP | [19-16] | y | |
b693d0b3 | 162 | +------------------------------+---------+---------+ |
4aa8a472 | 163 | | EL3 | [15-12] | n | |
b693d0b3 | 164 | +------------------------------+---------+---------+ |
4aa8a472 | 165 | | EL2 | [11-8] | n | |
b693d0b3 | 166 | +------------------------------+---------+---------+ |
4aa8a472 | 167 | | EL1 | [7-4] | n | |
b693d0b3 | 168 | +------------------------------+---------+---------+ |
4aa8a472 | 169 | | EL0 | [3-0] | n | |
b693d0b3 | 170 | +------------------------------+---------+---------+ |
4aa8a472 SP |
171 | |
172 | ||
ade12b86 DM |
173 | 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 |
174 | +------------------------------+---------+---------+ | |
175 | | Name | bits | visible | | |
176 | +------------------------------+---------+---------+ | |
177 | | SSBS | [7-4] | y | | |
178 | +------------------------------+---------+---------+ | |
b693d0b3 | 179 | |
b693d0b3 | 180 | |
ade12b86 | 181 | 4) MIDR_EL1 - Main ID Register |
b693d0b3 | 182 | +------------------------------+---------+---------+ |
4aa8a472 | 183 | | Name | bits | visible | |
b693d0b3 | 184 | +------------------------------+---------+---------+ |
4aa8a472 | 185 | | Implementer | [31-24] | y | |
b693d0b3 | 186 | +------------------------------+---------+---------+ |
4aa8a472 | 187 | | Variant | [23-20] | y | |
b693d0b3 | 188 | +------------------------------+---------+---------+ |
4aa8a472 | 189 | | Architecture | [19-16] | y | |
b693d0b3 | 190 | +------------------------------+---------+---------+ |
4aa8a472 | 191 | | PartNum | [15-4] | y | |
b693d0b3 | 192 | +------------------------------+---------+---------+ |
4aa8a472 | 193 | | Revision | [3-0] | y | |
b693d0b3 | 194 | +------------------------------+---------+---------+ |
4aa8a472 SP |
195 | |
196 | NOTE: The 'visible' fields of MIDR_EL1 will contain the value | |
197 | as available on the CPU where it is fetched and is not a system | |
198 | wide safe value. | |
199 | ||
ade12b86 | 200 | 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 |
c8c3798d | 201 | |
b693d0b3 | 202 | +------------------------------+---------+---------+ |
c8c3798d | 203 | | Name | bits | visible | |
b693d0b3 | 204 | +------------------------------+---------+---------+ |
d4209d8b SP |
205 | | I8MM | [55-52] | y | |
206 | +------------------------------+---------+---------+ | |
207 | | DGH | [51-48] | y | | |
208 | +------------------------------+---------+---------+ | |
209 | | BF16 | [47-44] | y | | |
210 | +------------------------------+---------+---------+ | |
478016c3 | 211 | | SB | [39-36] | y | |
a8613e70 | 212 | +------------------------------+---------+---------+ |
478016c3 | 213 | | FRINTTS | [35-32] | y | |
a8613e70 | 214 | +------------------------------+---------+---------+ |
fbedc599 | 215 | | GPI | [31-28] | y | |
b693d0b3 | 216 | +------------------------------+---------+---------+ |
fbedc599 | 217 | | GPA | [27-24] | y | |
b693d0b3 | 218 | +------------------------------+---------+---------+ |
c651aae5 | 219 | | LRCPC | [23-20] | y | |
b693d0b3 | 220 | +------------------------------+---------+---------+ |
cb567e79 | 221 | | FCMA | [19-16] | y | |
b693d0b3 | 222 | +------------------------------+---------+---------+ |
c8c3798d | 223 | | JSCVT | [15-12] | y | |
b693d0b3 | 224 | +------------------------------+---------+---------+ |
fbedc599 | 225 | | API | [11-8] | y | |
b693d0b3 | 226 | +------------------------------+---------+---------+ |
fbedc599 | 227 | | APA | [7-4] | y | |
b693d0b3 | 228 | +------------------------------+---------+---------+ |
7aac405e | 229 | | DPB | [3-0] | y | |
b693d0b3 | 230 | +------------------------------+---------+---------+ |
c8c3798d | 231 | |
ade12b86 | 232 | 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 |
7206dc93 | 233 | |
b693d0b3 | 234 | +------------------------------+---------+---------+ |
7206dc93 | 235 | | Name | bits | visible | |
b693d0b3 | 236 | +------------------------------+---------+---------+ |
7206dc93 | 237 | | AT | [35-32] | y | |
b693d0b3 | 238 | +------------------------------+---------+---------+ |
7206dc93 | 239 | |
ade12b86 | 240 | 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 |
06a916fe | 241 | |
b693d0b3 | 242 | +------------------------------+---------+---------+ |
06a916fe | 243 | | Name | bits | visible | |
b693d0b3 | 244 | +------------------------------+---------+---------+ |
d4209d8b SP |
245 | | F64MM | [59-56] | y | |
246 | +------------------------------+---------+---------+ | |
247 | | F32MM | [55-52] | y | | |
248 | +------------------------------+---------+---------+ | |
249 | | I8MM | [47-44] | y | | |
250 | +------------------------------+---------+---------+ | |
06a916fe | 251 | | SM4 | [43-40] | y | |
b693d0b3 | 252 | +------------------------------+---------+---------+ |
06a916fe | 253 | | SHA3 | [35-32] | y | |
b693d0b3 | 254 | +------------------------------+---------+---------+ |
d4209d8b SP |
255 | | BF16 | [23-20] | y | |
256 | +------------------------------+---------+---------+ | |
06a916fe | 257 | | BitPerm | [19-16] | y | |
b693d0b3 | 258 | +------------------------------+---------+---------+ |
06a916fe | 259 | | AES | [7-4] | y | |
b693d0b3 | 260 | +------------------------------+---------+---------+ |
06a916fe | 261 | | SVEVer | [3-0] | y | |
b693d0b3 | 262 | +------------------------------+---------+---------+ |
06a916fe | 263 | |
4aa8a472 | 264 | Appendix I: Example |
b693d0b3 MCC |
265 | ------------------- |
266 | ||
267 | :: | |
268 | ||
269 | /* | |
270 | * Sample program to demonstrate the MRS emulation ABI. | |
271 | * | |
272 | * Copyright (C) 2015-2016, ARM Ltd | |
273 | * | |
274 | * Author: Suzuki K Poulose <suzuki.poulose@arm.com> | |
275 | * | |
276 | * This program is free software; you can redistribute it and/or modify | |
277 | * it under the terms of the GNU General Public License version 2 as | |
278 | * published by the Free Software Foundation. | |
279 | * | |
280 | * This program is distributed in the hope that it will be useful, | |
281 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
282 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
283 | * GNU General Public License for more details. | |
284 | * This program is free software; you can redistribute it and/or modify | |
285 | * it under the terms of the GNU General Public License version 2 as | |
286 | * published by the Free Software Foundation. | |
287 | * | |
288 | * This program is distributed in the hope that it will be useful, | |
289 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
290 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
291 | * GNU General Public License for more details. | |
292 | */ | |
293 | ||
294 | #include <asm/hwcap.h> | |
295 | #include <stdio.h> | |
296 | #include <sys/auxv.h> | |
297 | ||
298 | #define get_cpu_ftr(id) ({ \ | |
4aa8a472 SP |
299 | unsigned long __val; \ |
300 | asm("mrs %0, "#id : "=r" (__val)); \ | |
301 | printf("%-20s: 0x%016lx\n", #id, __val); \ | |
302 | }) | |
303 | ||
b693d0b3 MCC |
304 | int main(void) |
305 | { | |
4aa8a472 SP |
306 | |
307 | if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { | |
308 | fputs("CPUID registers unavailable\n", stderr); | |
309 | return 1; | |
310 | } | |
311 | ||
312 | get_cpu_ftr(ID_AA64ISAR0_EL1); | |
313 | get_cpu_ftr(ID_AA64ISAR1_EL1); | |
314 | get_cpu_ftr(ID_AA64MMFR0_EL1); | |
315 | get_cpu_ftr(ID_AA64MMFR1_EL1); | |
316 | get_cpu_ftr(ID_AA64PFR0_EL1); | |
317 | get_cpu_ftr(ID_AA64PFR1_EL1); | |
318 | get_cpu_ftr(ID_AA64DFR0_EL1); | |
319 | get_cpu_ftr(ID_AA64DFR1_EL1); | |
320 | ||
321 | get_cpu_ftr(MIDR_EL1); | |
322 | get_cpu_ftr(MPIDR_EL1); | |
323 | get_cpu_ftr(REVIDR_EL1); | |
324 | ||
b693d0b3 | 325 | #if 0 |
4aa8a472 SP |
326 | /* Unexposed register access causes SIGILL */ |
327 | get_cpu_ftr(ID_MMFR0_EL1); | |
b693d0b3 | 328 | #endif |
4aa8a472 SP |
329 | |
330 | return 0; | |
b693d0b3 | 331 | } |