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326bc876 SF |
1 | ======================================================= |
2 | Semantics and Behavior of Atomic and Bitmask Operations | |
3 | ======================================================= | |
1da177e4 | 4 | |
326bc876 | 5 | :Author: David S. Miller |
1da177e4 | 6 | |
326bc876 | 7 | This document is intended to serve as a guide to Linux port |
1da177e4 LT |
8 | maintainers on how to implement atomic counter, bitops, and spinlock |
9 | interfaces properly. | |
10 | ||
326bc876 SF |
11 | Atomic Type And Operations |
12 | ========================== | |
13 | ||
14 | The atomic_t type should be defined as a signed integer and | |
1f7870dd PM |
15 | the atomic_long_t type as a signed long integer. Also, they should |
16 | be made opaque such that any kind of cast to a normal C integer type | |
326bc876 | 17 | will fail. Something like the following should suffice:: |
1da177e4 | 18 | |
72eef0f3 | 19 | typedef struct { int counter; } atomic_t; |
1f7870dd | 20 | typedef struct { long counter; } atomic_long_t; |
1da177e4 | 21 | |
8d7b52df | 22 | Historically, counter has been declared volatile. This is now discouraged. |
326bc876 SF |
23 | See :ref:`Documentation/process/volatile-considered-harmful.rst |
24 | <volatile_considered_harmful>` for the complete rationale. | |
8d7b52df | 25 | |
1a2142b0 GG |
26 | local_t is very similar to atomic_t. If the counter is per CPU and only |
27 | updated by one CPU, local_t is probably more appropriate. Please see | |
326bc876 SF |
28 | :ref:`Documentation/core-api/local_ops.rst <local_ops>` for the semantics of |
29 | local_t. | |
1a2142b0 | 30 | |
8d7b52df | 31 | The first operations to implement for atomic_t's are the initializers and |
326bc876 | 32 | plain reads. :: |
1da177e4 LT |
33 | |
34 | #define ATOMIC_INIT(i) { (i) } | |
35 | #define atomic_set(v, i) ((v)->counter = (i)) | |
36 | ||
326bc876 | 37 | The first macro is used in definitions, such as:: |
1da177e4 | 38 | |
326bc876 | 39 | static atomic_t my_counter = ATOMIC_INIT(1); |
1da177e4 | 40 | |
8d7b52df ML |
41 | The initializer is atomic in that the return values of the atomic operations |
42 | are guaranteed to be correct reflecting the initialized value if the | |
43 | initializer is used before runtime. If the initializer is used at runtime, a | |
44 | proper implicit or explicit read memory barrier is needed before reading the | |
45 | value with atomic_read from another thread. | |
46 | ||
326bc876 SF |
47 | As with all of the ``atomic_`` interfaces, replace the leading ``atomic_`` |
48 | with ``atomic_long_`` to operate on atomic_long_t. | |
1f7870dd | 49 | |
326bc876 | 50 | The second interface can be used at runtime, as in:: |
1da177e4 LT |
51 | |
52 | struct foo { atomic_t counter; }; | |
53 | ... | |
54 | ||
55 | struct foo *k; | |
56 | ||
57 | k = kmalloc(sizeof(*k), GFP_KERNEL); | |
58 | if (!k) | |
59 | return -ENOMEM; | |
60 | atomic_set(&k->counter, 0); | |
61 | ||
8d7b52df ML |
62 | The setting is atomic in that the return values of the atomic operations by |
63 | all threads are guaranteed to be correct reflecting either the value that has | |
64 | been set with this operation or set with another operation. A proper implicit | |
65 | or explicit memory barrier is needed before the value set with the operation | |
66 | is guaranteed to be readable with atomic_read from another thread. | |
67 | ||
326bc876 | 68 | Next, we have:: |
1da177e4 LT |
69 | |
70 | #define atomic_read(v) ((v)->counter) | |
71 | ||
8d7b52df ML |
72 | which simply reads the counter value currently visible to the calling thread. |
73 | The read is atomic in that the return value is guaranteed to be one of the | |
74 | values initialized or modified with the interface operations if a proper | |
75 | implicit or explicit memory barrier is used after possible runtime | |
76 | initialization by any other thread and the value is modified only with the | |
77 | interface operations. atomic_read does not guarantee that the runtime | |
78 | initialization by any other thread is visible yet, so the user of the | |
79 | interface must take care of that with a proper implicit or explicit memory | |
80 | barrier. | |
81 | ||
326bc876 | 82 | .. warning:: |
8d7b52df | 83 | |
326bc876 | 84 | ``atomic_read()`` and ``atomic_set()`` DO NOT IMPLY BARRIERS! |
8d7b52df | 85 | |
326bc876 SF |
86 | Some architectures may choose to use the volatile keyword, barriers, or |
87 | inline assembly to guarantee some degree of immediacy for atomic_read() | |
88 | and atomic_set(). This is not uniformly guaranteed, and may change in | |
89 | the future, so all users of atomic_t should treat atomic_read() and | |
90 | atomic_set() as simple C statements that may be reordered or optimized | |
91 | away entirely by the compiler or processor, and explicitly invoke the | |
92 | appropriate compiler and/or memory barrier for each use case. Failure | |
93 | to do so will result in code that may suddenly break when used with | |
94 | different architectures or compiler optimizations, or even changes in | |
95 | unrelated code which changes how the compiler optimizes the section | |
96 | accessing atomic_t variables. | |
8d7b52df | 97 | |
182dd4b2 PM |
98 | Properly aligned pointers, longs, ints, and chars (and unsigned |
99 | equivalents) may be atomically loaded from and stored to in the same | |
47f42122 MR |
100 | sense as described for atomic_read() and atomic_set(). The READ_ONCE() |
101 | and WRITE_ONCE() macros should be used to prevent the compiler from using | |
102 | optimizations that might otherwise optimize accesses out of existence on | |
103 | the one hand, or that might create unsolicited accesses on the other. | |
182dd4b2 | 104 | |
326bc876 | 105 | For example consider the following code:: |
182dd4b2 PM |
106 | |
107 | while (a > 0) | |
108 | do_something(); | |
109 | ||
110 | If the compiler can prove that do_something() does not store to the | |
111 | variable a, then the compiler is within its rights transforming this to | |
326bc876 | 112 | the following:: |
182dd4b2 PM |
113 | |
114 | tmp = a; | |
115 | if (a > 0) | |
116 | for (;;) | |
117 | do_something(); | |
118 | ||
119 | If you don't want the compiler to do this (and you probably don't), then | |
326bc876 | 120 | you should use something like the following:: |
182dd4b2 | 121 | |
47f42122 | 122 | while (READ_ONCE(a) < 0) |
182dd4b2 PM |
123 | do_something(); |
124 | ||
125 | Alternatively, you could place a barrier() call in the loop. | |
126 | ||
326bc876 | 127 | For another example, consider the following code:: |
182dd4b2 PM |
128 | |
129 | tmp_a = a; | |
130 | do_something_with(tmp_a); | |
131 | do_something_else_with(tmp_a); | |
132 | ||
133 | If the compiler can prove that do_something_with() does not store to the | |
134 | variable a, then the compiler is within its rights to manufacture an | |
326bc876 | 135 | additional load as follows:: |
182dd4b2 PM |
136 | |
137 | tmp_a = a; | |
138 | do_something_with(tmp_a); | |
139 | tmp_a = a; | |
140 | do_something_else_with(tmp_a); | |
141 | ||
142 | This could fatally confuse your code if it expected the same value | |
143 | to be passed to do_something_with() and do_something_else_with(). | |
144 | ||
145 | The compiler would be likely to manufacture this additional load if | |
146 | do_something_with() was an inline function that made very heavy use | |
147 | of registers: reloading from variable a could save a flush to the | |
148 | stack and later reload. To prevent the compiler from attacking your | |
326bc876 | 149 | code in this manner, write the following:: |
182dd4b2 | 150 | |
47f42122 | 151 | tmp_a = READ_ONCE(a); |
182dd4b2 PM |
152 | do_something_with(tmp_a); |
153 | do_something_else_with(tmp_a); | |
154 | ||
155 | For a final example, consider the following code, assuming that the | |
156 | variable a is set at boot time before the second CPU is brought online | |
326bc876 | 157 | and never changed later, so that memory barriers are not needed:: |
182dd4b2 PM |
158 | |
159 | if (a) | |
160 | b = 9; | |
161 | else | |
162 | b = 42; | |
163 | ||
164 | The compiler is within its rights to manufacture an additional store | |
326bc876 | 165 | by transforming the above code into the following:: |
182dd4b2 PM |
166 | |
167 | b = 42; | |
168 | if (a) | |
169 | b = 9; | |
170 | ||
171 | This could come as a fatal surprise to other code running concurrently | |
172 | that expected b to never have the value 42 if a was zero. To prevent | |
326bc876 | 173 | the compiler from doing this, write something like:: |
182dd4b2 PM |
174 | |
175 | if (a) | |
47f42122 | 176 | WRITE_ONCE(b, 9); |
182dd4b2 | 177 | else |
47f42122 | 178 | WRITE_ONCE(b, 42); |
182dd4b2 PM |
179 | |
180 | Don't even -think- about doing this without proper use of memory barriers, | |
181 | locks, or atomic operations if variable a can change at runtime! | |
182 | ||
326bc876 SF |
183 | .. warning:: |
184 | ||
185 | ``READ_ONCE()`` OR ``WRITE_ONCE()`` DO NOT IMPLY A BARRIER! | |
182dd4b2 | 186 | |
8d7b52df | 187 | Now, we move onto the atomic operation interfaces typically implemented with |
326bc876 | 188 | the help of assembly code. :: |
1da177e4 LT |
189 | |
190 | void atomic_add(int i, atomic_t *v); | |
191 | void atomic_sub(int i, atomic_t *v); | |
192 | void atomic_inc(atomic_t *v); | |
193 | void atomic_dec(atomic_t *v); | |
194 | ||
195 | These four routines add and subtract integral values to/from the given | |
196 | atomic_t value. The first two routines pass explicit integers by | |
197 | which to make the adjustment, whereas the latter two use an implicit | |
198 | adjustment value of "1". | |
199 | ||
200 | One very important aspect of these two routines is that they DO NOT | |
201 | require any explicit memory barriers. They need only perform the | |
202 | atomic_t counter update in an SMP safe manner. | |
203 | ||
326bc876 | 204 | Next, we have:: |
1da177e4 LT |
205 | |
206 | int atomic_inc_return(atomic_t *v); | |
207 | int atomic_dec_return(atomic_t *v); | |
208 | ||
209 | These routines add 1 and subtract 1, respectively, from the given | |
210 | atomic_t and return the new counter value after the operation is | |
211 | performed. | |
212 | ||
daf1aab9 PM |
213 | Unlike the above routines, it is required that these primitives |
214 | include explicit memory barriers that are performed before and after | |
215 | the operation. It must be done such that all memory operations before | |
216 | and after the atomic operation calls are strongly ordered with respect | |
217 | to the atomic operation itself. | |
1da177e4 LT |
218 | |
219 | For example, it should behave as if a smp_mb() call existed both | |
220 | before and after the atomic operation. | |
221 | ||
222 | If the atomic instructions used in an implementation provide explicit | |
223 | memory barrier semantics which satisfy the above requirements, that is | |
224 | fine as well. | |
225 | ||
326bc876 | 226 | Let's move on:: |
1da177e4 LT |
227 | |
228 | int atomic_add_return(int i, atomic_t *v); | |
229 | int atomic_sub_return(int i, atomic_t *v); | |
230 | ||
231 | These behave just like atomic_{inc,dec}_return() except that an | |
232 | explicit counter adjustment is given instead of the implicit "1". | |
233 | This means that like atomic_{inc,dec}_return(), the memory barrier | |
234 | semantics are required. | |
235 | ||
326bc876 | 236 | Next:: |
1da177e4 LT |
237 | |
238 | int atomic_inc_and_test(atomic_t *v); | |
239 | int atomic_dec_and_test(atomic_t *v); | |
240 | ||
241 | These two routines increment and decrement by 1, respectively, the | |
242 | given atomic counter. They return a boolean indicating whether the | |
243 | resulting counter value was zero or not. | |
244 | ||
daf1aab9 | 245 | Again, these primitives provide explicit memory barrier semantics around |
326bc876 | 246 | the atomic operation:: |
1da177e4 LT |
247 | |
248 | int atomic_sub_and_test(int i, atomic_t *v); | |
249 | ||
250 | This is identical to atomic_dec_and_test() except that an explicit | |
daf1aab9 | 251 | decrement is given instead of the implicit "1". This primitive must |
326bc876 | 252 | provide explicit memory barrier semantics around the operation:: |
1da177e4 LT |
253 | |
254 | int atomic_add_negative(int i, atomic_t *v); | |
255 | ||
daf1aab9 PM |
256 | The given increment is added to the given atomic counter value. A boolean |
257 | is return which indicates whether the resulting counter value is negative. | |
258 | This primitive must provide explicit memory barrier semantics around | |
259 | the operation. | |
1da177e4 | 260 | |
326bc876 | 261 | Then:: |
4a6dae6d | 262 | |
8d7b52df ML |
263 | int atomic_xchg(atomic_t *v, int new); |
264 | ||
265 | This performs an atomic exchange operation on the atomic variable v, setting | |
266 | the given new value. It returns the old value that the atomic variable v had | |
267 | just before the operation. | |
268 | ||
326bc876 | 269 | atomic_xchg must provide explicit memory barriers around the operation. :: |
7e8b1e78 | 270 | |
4a6dae6d NP |
271 | int atomic_cmpxchg(atomic_t *v, int old, int new); |
272 | ||
273 | This performs an atomic compare exchange operation on the atomic value v, | |
274 | with the given old and new values. Like all atomic_xxx operations, | |
275 | atomic_cmpxchg will only satisfy its atomicity semantics as long as all | |
326bc876 | 276 | other accesses of \*v are performed through atomic_xxx operations. |
4a6dae6d | 277 | |
ed2de9f7 WD |
278 | atomic_cmpxchg must provide explicit memory barriers around the operation, |
279 | although if the comparison fails then no memory ordering guarantees are | |
280 | required. | |
4a6dae6d NP |
281 | |
282 | The semantics for atomic_cmpxchg are the same as those defined for 'cas' | |
283 | below. | |
284 | ||
326bc876 | 285 | Finally:: |
8426e1f6 NP |
286 | |
287 | int atomic_add_unless(atomic_t *v, int a, int u); | |
288 | ||
289 | If the atomic value v is not equal to u, this function adds a to v, and | |
290 | returns non zero. If v is equal to u then it returns zero. This is done as | |
291 | an atomic operation. | |
292 | ||
daf1aab9 PM |
293 | atomic_add_unless must provide explicit memory barriers around the |
294 | operation unless it fails (returns 0). | |
8426e1f6 NP |
295 | |
296 | atomic_inc_not_zero, equivalent to atomic_add_unless(v, 1, 0) | |
297 | ||
4a6dae6d | 298 | |
1da177e4 LT |
299 | If a caller requires memory barrier semantics around an atomic_t |
300 | operation which does not return a value, a set of interfaces are | |
326bc876 | 301 | defined which accomplish this:: |
1da177e4 | 302 | |
1b15611e PZ |
303 | void smp_mb__before_atomic(void); |
304 | void smp_mb__after_atomic(void); | |
1da177e4 | 305 | |
326bc876 | 306 | For example, smp_mb__before_atomic() can be used like so:: |
1da177e4 LT |
307 | |
308 | obj->dead = 1; | |
1b15611e | 309 | smp_mb__before_atomic(); |
1da177e4 LT |
310 | atomic_dec(&obj->ref_count); |
311 | ||
a0ebb3ff | 312 | It makes sure that all memory operations preceding the atomic_dec() |
1da177e4 | 313 | call are strongly ordered with respect to the atomic counter |
a0ebb3ff | 314 | operation. In the above example, it guarantees that the assignment of |
1da177e4 LT |
315 | "1" to obj->dead will be globally visible to other cpus before the |
316 | atomic counter decrement. | |
317 | ||
1b15611e | 318 | Without the explicit smp_mb__before_atomic() call, the |
1da177e4 LT |
319 | implementation could legally allow the atomic counter update visible |
320 | to other cpus before the "obj->dead = 1;" assignment. | |
321 | ||
1da177e4 | 322 | A missing memory barrier in the cases where they are required by the |
a0ebb3ff MH |
323 | atomic_t implementation above can have disastrous results. Here is |
324 | an example, which follows a pattern occurring frequently in the Linux | |
1da177e4 LT |
325 | kernel. It is the use of atomic counters to implement reference |
326 | counting, and it works such that once the counter falls to zero it can | |
326bc876 SF |
327 | be guaranteed that no other entity can be accessing the object:: |
328 | ||
329 | static void obj_list_add(struct obj *obj, struct list_head *head) | |
330 | { | |
331 | obj->active = 1; | |
332 | list_add(&obj->list, head); | |
333 | } | |
334 | ||
335 | static void obj_list_del(struct obj *obj) | |
336 | { | |
337 | list_del(&obj->list); | |
338 | obj->active = 0; | |
339 | } | |
1da177e4 | 340 | |
326bc876 SF |
341 | static void obj_destroy(struct obj *obj) |
342 | { | |
343 | BUG_ON(obj->active); | |
344 | kfree(obj); | |
1da177e4 | 345 | } |
1da177e4 | 346 | |
326bc876 SF |
347 | struct obj *obj_list_peek(struct list_head *head) |
348 | { | |
349 | if (!list_empty(head)) { | |
350 | struct obj *obj; | |
351 | ||
352 | obj = list_entry(head->next, struct obj, list); | |
353 | atomic_inc(&obj->refcnt); | |
354 | return obj; | |
355 | } | |
356 | return NULL; | |
357 | } | |
358 | ||
359 | void obj_poke(void) | |
360 | { | |
361 | struct obj *obj; | |
362 | ||
363 | spin_lock(&global_list_lock); | |
364 | obj = obj_list_peek(&global_list); | |
365 | spin_unlock(&global_list_lock); | |
1da177e4 | 366 | |
326bc876 SF |
367 | if (obj) { |
368 | obj->ops->poke(obj); | |
369 | if (atomic_dec_and_test(&obj->refcnt)) | |
370 | obj_destroy(obj); | |
371 | } | |
372 | } | |
373 | ||
374 | void obj_timeout(struct obj *obj) | |
375 | { | |
376 | spin_lock(&global_list_lock); | |
377 | obj_list_del(obj); | |
378 | spin_unlock(&global_list_lock); | |
1da177e4 | 379 | |
1da177e4 LT |
380 | if (atomic_dec_and_test(&obj->refcnt)) |
381 | obj_destroy(obj); | |
382 | } | |
1da177e4 | 383 | |
326bc876 | 384 | .. note:: |
1da177e4 | 385 | |
326bc876 SF |
386 | This is a simplification of the ARP queue management in the generic |
387 | neighbour discover code of the networking. Olaf Kirch found a bug wrt. | |
388 | memory barriers in kfree_skb() that exposed the atomic_t memory barrier | |
389 | requirements quite clearly. | |
1da177e4 LT |
390 | |
391 | Given the above scheme, it must be the case that the obj->active | |
392 | update done by the obj list deletion be visible to other processors | |
393 | before the atomic counter decrement is performed. | |
394 | ||
395 | Otherwise, the counter could fall to zero, yet obj->active would still | |
396 | be set, thus triggering the assertion in obj_destroy(). The error | |
326bc876 | 397 | sequence looks like this:: |
1da177e4 LT |
398 | |
399 | cpu 0 cpu 1 | |
400 | obj_poke() obj_timeout() | |
401 | obj = obj_list_peek(); | |
402 | ... gains ref to obj, refcnt=2 | |
403 | obj_list_del(obj); | |
404 | obj->active = 0 ... | |
405 | ... visibility delayed ... | |
406 | atomic_dec_and_test() | |
407 | ... refcnt drops to 1 ... | |
408 | atomic_dec_and_test() | |
409 | ... refcount drops to 0 ... | |
410 | obj_destroy() | |
411 | BUG() triggers since obj->active | |
412 | still seen as one | |
413 | obj->active update visibility occurs | |
414 | ||
415 | With the memory barrier semantics required of the atomic_t operations | |
416 | which return values, the above sequence of memory visibility can never | |
417 | happen. Specifically, in the above case the atomic_dec_and_test() | |
418 | counter decrement would not become globally visible until the | |
419 | obj->active update does. | |
420 | ||
421 | As a historical note, 32-bit Sparc used to only allow usage of | |
a33f3224 | 422 | 24-bits of its atomic_t type. This was because it used 8 bits |
1da177e4 LT |
423 | as a spinlock for SMP safety. Sparc32 lacked a "compare and swap" |
424 | type instruction. However, 32-bit Sparc has since been moved over | |
425 | to a "hash table of spinlocks" scheme, that allows the full 32-bit | |
426 | counter to be realized. Essentially, an array of spinlocks are | |
427 | indexed into based upon the address of the atomic_t being operated | |
428 | on, and that lock protects the atomic operation. Parisc uses the | |
429 | same scheme. | |
430 | ||
431 | Another note is that the atomic_t operations returning values are | |
432 | extremely slow on an old 386. | |
433 | ||
326bc876 SF |
434 | |
435 | Atomic Bitmask | |
436 | ============== | |
437 | ||
1da177e4 LT |
438 | We will now cover the atomic bitmask operations. You will find that |
439 | their SMP and memory barrier semantics are similar in shape and scope | |
440 | to the atomic_t ops above. | |
441 | ||
442 | Native atomic bit operations are defined to operate on objects aligned | |
443 | to the size of an "unsigned long" C data type, and are least of that | |
444 | size. The endianness of the bits within each "unsigned long" are the | |
326bc876 | 445 | native endianness of the cpu. :: |
1da177e4 | 446 | |
a0ebb3ff MH |
447 | void set_bit(unsigned long nr, volatile unsigned long *addr); |
448 | void clear_bit(unsigned long nr, volatile unsigned long *addr); | |
449 | void change_bit(unsigned long nr, volatile unsigned long *addr); | |
1da177e4 LT |
450 | |
451 | These routines set, clear, and change, respectively, the bit number | |
452 | indicated by "nr" on the bit mask pointed to by "ADDR". | |
453 | ||
454 | They must execute atomically, yet there are no implicit memory barrier | |
326bc876 | 455 | semantics required of these interfaces. :: |
1da177e4 | 456 | |
a0ebb3ff MH |
457 | int test_and_set_bit(unsigned long nr, volatile unsigned long *addr); |
458 | int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr); | |
459 | int test_and_change_bit(unsigned long nr, volatile unsigned long *addr); | |
1da177e4 LT |
460 | |
461 | Like the above, except that these routines return a boolean which | |
462 | indicates whether the changed bit was set _BEFORE_ the atomic bit | |
463 | operation. | |
464 | ||
465 | WARNING! It is incredibly important that the value be a boolean, | |
466 | ie. "0" or "1". Do not try to be fancy and save a few instructions by | |
467 | declaring the above to return "long" and just returning something like | |
468 | "old_val & mask" because that will not work. | |
469 | ||
470 | For one thing, this return value gets truncated to int in many code | |
471 | paths using these interfaces, so on 64-bit if the bit is set in the | |
472 | upper 32-bits then testers will never see that. | |
473 | ||
474 | One great example of where this problem crops up are the thread_info | |
475 | flag operations. Routines such as test_and_set_ti_thread_flag() chop | |
476 | the return value into an int. There are other places where things | |
477 | like this occur as well. | |
478 | ||
479 | These routines, like the atomic_t counter operations returning values, | |
daf1aab9 PM |
480 | must provide explicit memory barrier semantics around their execution. |
481 | All memory operations before the atomic bit operation call must be | |
482 | made visible globally before the atomic bit operation is made visible. | |
1da177e4 | 483 | Likewise, the atomic bit operation must be visible globally before any |
326bc876 | 484 | subsequent memory operation is made visible. For example:: |
1da177e4 LT |
485 | |
486 | obj->dead = 1; | |
487 | if (test_and_set_bit(0, &obj->flags)) | |
488 | /* ... */; | |
489 | obj->killed = 1; | |
490 | ||
a0ebb3ff | 491 | The implementation of test_and_set_bit() must guarantee that |
1da177e4 LT |
492 | "obj->dead = 1;" is visible to cpus before the atomic memory operation |
493 | done by test_and_set_bit() becomes visible. Likewise, the atomic | |
494 | memory operation done by test_and_set_bit() must become visible before | |
495 | "obj->killed = 1;" is visible. | |
496 | ||
326bc876 | 497 | Finally there is the basic operation:: |
1da177e4 LT |
498 | |
499 | int test_bit(unsigned long nr, __const__ volatile unsigned long *addr); | |
500 | ||
501 | Which returns a boolean indicating if bit "nr" is set in the bitmask | |
502 | pointed to by "addr". | |
503 | ||
1b15611e PZ |
504 | If explicit memory barriers are required around {set,clear}_bit() (which do |
505 | not return a value, and thus does not need to provide memory barrier | |
326bc876 | 506 | semantics), two interfaces are provided:: |
1da177e4 | 507 | |
1b15611e PZ |
508 | void smp_mb__before_atomic(void); |
509 | void smp_mb__after_atomic(void); | |
1da177e4 LT |
510 | |
511 | They are used as follows, and are akin to their atomic_t operation | |
326bc876 | 512 | brothers:: |
1da177e4 LT |
513 | |
514 | /* All memory operations before this call will | |
515 | * be globally visible before the clear_bit(). | |
516 | */ | |
1b15611e | 517 | smp_mb__before_atomic(); |
1da177e4 LT |
518 | clear_bit( ... ); |
519 | ||
520 | /* The clear_bit() will be visible before all | |
521 | * subsequent memory operations. | |
522 | */ | |
1b15611e | 523 | smp_mb__after_atomic(); |
1da177e4 | 524 | |
26333576 NP |
525 | There are two special bitops with lock barrier semantics (acquire/release, |
526 | same as spinlocks). These operate in the same way as their non-_lock/unlock | |
527 | postfixed variants, except that they are to provide acquire/release semantics, | |
528 | respectively. This means they can be used for bit_spin_trylock and | |
326bc876 | 529 | bit_spin_unlock type operations without specifying any more barriers. :: |
26333576 NP |
530 | |
531 | int test_and_set_bit_lock(unsigned long nr, unsigned long *addr); | |
532 | void clear_bit_unlock(unsigned long nr, unsigned long *addr); | |
533 | void __clear_bit_unlock(unsigned long nr, unsigned long *addr); | |
534 | ||
535 | The __clear_bit_unlock version is non-atomic, however it still implements | |
536 | unlock barrier semantics. This can be useful if the lock itself is protecting | |
537 | the other bits in the word. | |
538 | ||
1da177e4 LT |
539 | Finally, there are non-atomic versions of the bitmask operations |
540 | provided. They are used in contexts where some other higher-level SMP | |
541 | locking scheme is being used to protect the bitmask, and thus less | |
542 | expensive non-atomic operations may be used in the implementation. | |
543 | They have names similar to the above bitmask operation interfaces, | |
326bc876 | 544 | except that two underscores are prefixed to the interface name. :: |
1da177e4 LT |
545 | |
546 | void __set_bit(unsigned long nr, volatile unsigned long *addr); | |
547 | void __clear_bit(unsigned long nr, volatile unsigned long *addr); | |
548 | void __change_bit(unsigned long nr, volatile unsigned long *addr); | |
549 | int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr); | |
550 | int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr); | |
551 | int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr); | |
552 | ||
553 | These non-atomic variants also do not require any special memory | |
554 | barrier semantics. | |
555 | ||
daf1aab9 PM |
556 | The routines xchg() and cmpxchg() must provide the same exact |
557 | memory-barrier semantics as the atomic and bit operations returning | |
558 | values. | |
1da177e4 | 559 | |
326bc876 SF |
560 | .. note:: |
561 | ||
562 | If someone wants to use xchg(), cmpxchg() and their variants, | |
563 | linux/atomic.h should be included rather than asm/cmpxchg.h, unless the | |
564 | code is in arch/* and can take care of itself. | |
84567995 | 565 | |
1da177e4 LT |
566 | Spinlocks and rwlocks have memory barrier expectations as well. |
567 | The rule to follow is simple: | |
568 | ||
569 | 1) When acquiring a lock, the implementation must make it globally | |
570 | visible before any subsequent memory operation. | |
571 | ||
572 | 2) When releasing a lock, the implementation must make it such that | |
573 | all previous memory operations are globally visible before the | |
574 | lock release. | |
575 | ||
576 | Which finally brings us to _atomic_dec_and_lock(). There is an | |
577 | architecture-neutral version implemented in lib/dec_and_lock.c, | |
326bc876 | 578 | but most platforms will wish to optimize this in assembler. :: |
1da177e4 LT |
579 | |
580 | int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock); | |
581 | ||
582 | Atomically decrement the given counter, and if will drop to zero | |
583 | atomically acquire the given spinlock and perform the decrement | |
584 | of the counter to zero. If it does not drop to zero, do nothing | |
585 | with the spinlock. | |
586 | ||
587 | It is actually pretty simple to get the memory barrier correct. | |
588 | Simply satisfy the spinlock grab requirements, which is make | |
589 | sure the spinlock operation is globally visible before any | |
590 | subsequent memory operation. | |
591 | ||
592 | We can demonstrate this operation more clearly if we define | |
326bc876 | 593 | an abstract atomic operation:: |
1da177e4 LT |
594 | |
595 | long cas(long *mem, long old, long new); | |
596 | ||
597 | "cas" stands for "compare and swap". It atomically: | |
598 | ||
599 | 1) Compares "old" with the value currently at "mem". | |
600 | 2) If they are equal, "new" is written to "mem". | |
601 | 3) Regardless, the current value at "mem" is returned. | |
602 | ||
603 | As an example usage, here is what an atomic counter update | |
326bc876 | 604 | might look like:: |
1da177e4 | 605 | |
326bc876 SF |
606 | void example_atomic_inc(long *counter) |
607 | { | |
608 | long old, new, ret; | |
1da177e4 | 609 | |
326bc876 SF |
610 | while (1) { |
611 | old = *counter; | |
612 | new = old + 1; | |
1da177e4 | 613 | |
326bc876 SF |
614 | ret = cas(counter, old, new); |
615 | if (ret == old) | |
616 | break; | |
1da177e4 LT |
617 | } |
618 | } | |
619 | ||
326bc876 SF |
620 | Let's use cas() in order to build a pseudo-C atomic_dec_and_lock():: |
621 | ||
622 | int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock) | |
623 | { | |
624 | long old, new, ret; | |
625 | int went_to_zero; | |
626 | ||
627 | went_to_zero = 0; | |
628 | while (1) { | |
629 | old = atomic_read(atomic); | |
630 | new = old - 1; | |
631 | if (new == 0) { | |
632 | went_to_zero = 1; | |
633 | spin_lock(lock); | |
634 | } | |
635 | ret = cas(atomic, old, new); | |
636 | if (ret == old) | |
637 | break; | |
638 | if (went_to_zero) { | |
639 | spin_unlock(lock); | |
640 | went_to_zero = 0; | |
641 | } | |
642 | } | |
643 | ||
644 | return went_to_zero; | |
645 | } | |
1da177e4 LT |
646 | |
647 | Now, as far as memory barriers go, as long as spin_lock() | |
648 | strictly orders all subsequent memory operations (including | |
649 | the cas()) with respect to itself, things will be fine. | |
650 | ||
a0ebb3ff | 651 | Said another way, _atomic_dec_and_lock() must guarantee that |
1da177e4 LT |
652 | a counter dropping to zero is never made visible before the |
653 | spinlock being acquired. | |
654 | ||
326bc876 SF |
655 | .. note:: |
656 | ||
657 | Note that this also means that for the case where the counter is not | |
658 | dropping to zero, there are no memory ordering requirements. |