projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e660e5c TP |
1 | Marvell Armada CP110 System Controller 0 |
| 2 | ======================================== | |
| 3 | ||
| 4 | The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K | |
| 5 | SoCs. It contains two sets of system control registers, System | |
| 6 | Controller 0 and System Controller 1. This Device Tree binding allows | |
| 7 | to describe the first system controller, which provides registers to | |
| 8 | configure various aspects of the SoC. | |
| 9 | ||
| 10 | The Device Tree node representing this System Controller 0 provides a | |
| 11 | number of clocks: | |
| 12 | ||
| 13 | - a set of core clocks | |
| 14 | - a set of gatable clocks | |
| 15 | ||
| 16 | Those clocks can be referenced by other Device Tree nodes using two | |
| 17 | cells: | |
| 18 | - The first cell must be 0 or 1. 0 for the core clocks and 1 for the | |
| 19 | gatable clocks. | |
| 20 | - The second cell identifies the particular core clock or gatable | |
| 21 | clocks. | |
| 22 | ||
| 23 | The following clocks are available: | |
| 24 | - Core clocks | |
| 25 | - 0 0 APLL | |
| 26 | - 0 1 PPv2 core | |
| 27 | - 0 2 EIP | |
| 28 | - 0 3 Core | |
| 29 | - 0 4 NAND core | |
| 30 | - Gatable clocks | |
| 31 | - 1 0 Audio | |
| 32 | - 1 1 Comm Unit | |
| 33 | - 1 2 NAND | |
| 34 | - 1 3 PPv2 | |
| 35 | - 1 4 SDIO | |
| 36 | - 1 5 MG Domain | |
| 37 | - 1 6 MG Core | |
| 38 | - 1 7 XOR1 | |
| 39 | - 1 8 XOR0 | |
| 40 | - 1 9 GOP DP | |
| 41 | - 1 11 PCIe x1 0 | |
| 42 | - 1 12 PCIe x1 1 | |
| 43 | - 1 13 PCIe x4 | |
| 44 | - 1 14 PCIe / XOR | |
| 45 | - 1 15 SATA | |
| 46 | - 1 16 SATA USB | |
| 47 | - 1 17 Main | |
| cda82ace | 48 | - 1 18 SD/MMC/GOP |
| 6e660e5c TP |
49 | - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) |
| 50 | - 1 22 USB3H0 | |
| 51 | - 1 23 USB3H1 | |
| 52 | - 1 24 USB3 Device | |
| 53 | - 1 25 EIP150 | |
| 54 | - 1 26 EIP197 | |
| 55 | ||
| 56 | Required properties: | |
| 57 | ||
| 58 | - compatible: must be: | |
| 59 | "marvell,cp110-system-controller0", "syscon"; | |
| 60 | - reg: register area of the CP110 system controller 0 | |
| 61 | - #clock-cells: must be set to 2 | |
| 62 | - core-clock-output-names must be set to: | |
| 63 | "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" | |
| 64 | - gate-clock-output-names must be set to: | |
| 65 | "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", | |
| 66 | "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", | |
| 67 | "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", | |
| cda82ace | 68 | "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", |
| 6e660e5c TP |
69 | "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; |
| 70 | ||
| 71 | Example: | |
| 72 | ||
| 73 | cpm_syscon0: system-controller@440000 { | |
| 74 | compatible = "marvell,cp110-system-controller0", "syscon"; | |
| 75 | reg = <0x440000 0x1000>; | |
| 76 | #clock-cells = <2>; | |
| 77 | core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"; | |
| 78 | gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", | |
| 79 | "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", | |
| 80 | "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", | |
| cda82ace | 81 | "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", |
| 6e660e5c TP |
82 | "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; |
| 83 | }; |