]>
Commit | Line | Data |
---|---|---|
808ecf4a SW |
1 | MediaTek AUDSYS controller |
2 | ============================ | |
3 | ||
4 | The MediaTek AUDSYS controller provides various clocks to the system. | |
5 | ||
6 | Required Properties: | |
7 | ||
8 | - compatible: Should be one of: | |
9cb12501 | 9 | - "mediatek,mt2701-audsys", "syscon" |
808ecf4a | 10 | - "mediatek,mt7622-audsys", "syscon" |
fd2a9f18 | 11 | - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" |
808ecf4a SW |
12 | - #clock-cells: Must be 1 |
13 | ||
14 | The AUDSYS controller uses the common clk binding from | |
15 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
16 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. | |
17 | ||
2817a92d RL |
18 | Required sub-nodes: |
19 | ------- | |
20 | For common binding part and usage, refer to | |
21 | ../sonud/mt2701-afe-pcm.txt. | |
22 | ||
808ecf4a SW |
23 | Example: |
24 | ||
2817a92d RL |
25 | audsys: clock-controller@11220000 { |
26 | compatible = "mediatek,mt7622-audsys", "syscon"; | |
27 | reg = <0 0x11220000 0 0x2000>; | |
28 | #clock-cells = <1>; | |
29 | ||
30 | afe: audio-controller { | |
31 | ... | |
32 | }; | |
33 | }; |