]>
Commit | Line | Data |
---|---|---|
808ecf4a SW |
1 | MediaTek AUDSYS controller |
2 | ============================ | |
3 | ||
4 | The MediaTek AUDSYS controller provides various clocks to the system. | |
5 | ||
6 | Required Properties: | |
7 | ||
8 | - compatible: Should be one of: | |
9cb12501 | 9 | - "mediatek,mt2701-audsys", "syscon" |
171f68a3 | 10 | - "mediatek,mt6779-audio", "syscon" |
808ecf4a | 11 | - "mediatek,mt7622-audsys", "syscon" |
fd2a9f18 | 12 | - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" |
2f41cd9b | 13 | - "mediatek,mt8183-audiosys", "syscon" |
3d8b6e9c | 14 | - "mediatek,mt8516-audsys", "syscon" |
808ecf4a SW |
15 | - #clock-cells: Must be 1 |
16 | ||
17 | The AUDSYS controller uses the common clk binding from | |
18 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
19 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. | |
20 | ||
2817a92d RL |
21 | Required sub-nodes: |
22 | ------- | |
23 | For common binding part and usage, refer to | |
24 | ../sonud/mt2701-afe-pcm.txt. | |
25 | ||
808ecf4a SW |
26 | Example: |
27 | ||
2817a92d RL |
28 | audsys: clock-controller@11220000 { |
29 | compatible = "mediatek,mt7622-audsys", "syscon"; | |
30 | reg = <0 0x11220000 0 0x2000>; | |
31 | #clock-cells = <1>; | |
32 | ||
33 | afe: audio-controller { | |
34 | ... | |
35 | }; | |
36 | }; |