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Commit | Line | Data |
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6a588703 JL |
1 | Mediatek ethsys controller |
2 | ============================ | |
3 | ||
4 | The Mediatek ethsys controller provides various clocks to the system. | |
5 | ||
6 | Required Properties: | |
7 | ||
8 | - compatible: Should be: | |
9 | - "mediatek,mt2701-ethsys", "syscon" | |
808ecf4a | 10 | - "mediatek,mt7622-ethsys", "syscon" |
fd2a9f18 | 11 | - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" |
6a588703 | 12 | - #clock-cells: Must be 1 |
2c97fa22 | 13 | - #reset-cells: Must be 1 |
6a588703 JL |
14 | |
15 | The ethsys controller uses the common clk binding from | |
16 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
17 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. | |
18 | ||
19 | Example: | |
20 | ||
21 | ethsys: clock-controller@1b000000 { | |
22 | compatible = "mediatek,mt2701-ethsys", "syscon"; | |
23 | reg = <0 0x1b000000 0 0x1000>; | |
24 | #clock-cells = <1>; | |
a227cf4d | 25 | #reset-cells = <1>; |
6a588703 | 26 | }; |