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Commit | Line | Data |
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96ca848e S |
1 | Some socs have a large number of interrupts requests to service |
2 | the needs of its many peripherals and subsystems. All of the | |
3 | interrupt lines from the subsystems are not needed at the same | |
4 | time, so they have to be muxed to the irq-controller appropriately. | |
5 | In such places a interrupt controllers are preceded by an CROSSBAR | |
6 | that provides flexibility in muxing the device requests to the controller | |
7 | inputs. | |
8 | ||
9 | Required properties: | |
10 | - compatible : Should be "ti,irq-crossbar" | |
11 | - reg: Base address and the size of the crossbar registers. | |
1e7449ba MZ |
12 | - interrupt-controller: indicates that this block is an interrupt controller. |
13 | - interrupt-parent: the interrupt controller this block is connected to. | |
14 | - ti,max-irqs: Total number of irqs available at the parent interrupt controller. | |
2f7d2fb7 | 15 | - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. |
96ca848e S |
16 | - ti,reg-size: Size of a individual register in bytes. Every individual |
17 | register is assumed to be of same size. Valid sizes are 1, 2, 4. | |
18 | - ti,irqs-reserved: List of the reserved irq lines that are not muxed using | |
19 | crossbar. These interrupt lines are reserved in the soc, | |
20 | so crossbar bar driver should not consider them as free | |
21 | lines. | |
22 | ||
64e0f8ba NM |
23 | Optional properties: |
24 | - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for | |
25 | SOC-specific hard-wiring of those irqs which unexpectedly bypasses the | |
26 | crossbar. These irqs have a crossbar register, but still cannot be used. | |
27 | ||
a35057d1 NM |
28 | - ti,irqs-safe-map: integer which maps to a safe configuration to use |
29 | when the interrupt controller irq is unused (when not provided, default is 0) | |
30 | ||
96ca848e | 31 | Examples: |
1e7449ba | 32 | crossbar_mpu: crossbar@4a002a48 { |
96ca848e S |
33 | compatible = "ti,irq-crossbar"; |
34 | reg = <0x4a002a48 0x130>; | |
35 | ti,max-irqs = <160>; | |
2f7d2fb7 | 36 | ti,max-crossbar-sources = <400>; |
96ca848e | 37 | ti,reg-size = <2>; |
1e7449ba | 38 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
64e0f8ba | 39 | ti,irqs-skip = <10 133 139 140>; |
96ca848e | 40 | }; |
9a34f73f NM |
41 | |
42 | Consumer: | |
43 | ======== | |
44 | See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and | |
45 | Documentation/devicetree/bindings/arm/gic.txt for further details. | |
46 | ||
47 | An interrupt consumer on an SoC using crossbar will use: | |
48 | interrupts = <GIC_SPI request_number interrupt_level> | |
9a34f73f NM |
49 | |
50 | Example: | |
51 | device_x@0x4a023000 { | |
52 | /* Crossbar 8 used */ | |
53 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
54 | ... | |
55 | }; |