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1241ef94 PV |
1 | * Samsung Audio Subsystem Clock Controller |
2 | ||
3 | The Samsung Audio Subsystem clock controller generates and supplies clocks | |
4 | to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock | |
30abda17 | 5 | binding described here is applicable to all SoCs in Exynos family. |
1241ef94 PV |
6 | |
7 | Required Properties: | |
8 | ||
9 | - compatible: should be one of the following: | |
10 | - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. | |
3538a2cf AB |
11 | - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 |
12 | SoCs. | |
2ec865b7 SN |
13 | - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410 |
14 | SoCs. | |
3538a2cf AB |
15 | - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 |
16 | SoCs. | |
1241ef94 PV |
17 | - reg: physical base address and length of the controller's register set. |
18 | ||
19 | - #clock-cells: should be 1. | |
20 | ||
547f3350 AB |
21 | - clocks: |
22 | - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" | |
23 | is used if not specified. | |
24 | - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" | |
25 | is used if not specified. | |
26 | - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not | |
27 | specified. | |
28 | - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if | |
29 | not specified. | |
30 | - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not | |
31 | specified. | |
32 | ||
33 | - clock-names: Aliases for the above clocks. They should be "pll_ref", | |
34 | "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. | |
35 | ||
1241ef94 PV |
36 | The following is the list of clocks generated by the controller. Each clock is |
37 | assigned an identifier and client nodes use this identifier to specify the | |
38 | clock which they consume. Some of the clocks are available only on a particular | |
39 | Exynos4 SoC and this is specified where applicable. | |
40 | ||
41 | Provided clocks: | |
42 | ||
43 | Clock ID SoC (if specific) | |
44 | ----------------------------------------------- | |
45 | ||
46 | mout_audss 0 | |
47 | mout_i2s 1 | |
48 | dout_srp 2 | |
49 | dout_aud_bus 3 | |
50 | dout_i2s 4 | |
51 | srp_clk 5 | |
52 | i2s_bus 6 | |
53 | sclk_i2s 7 | |
54 | pcm_bus 8 | |
55 | sclk_pcm 9 | |
3538a2cf | 56 | adma 10 Exynos5420 |
1241ef94 | 57 | |
547f3350 AB |
58 | Example 1: An example of a clock controller node using the default input |
59 | clock names is listed below. | |
60 | ||
61 | clock_audss: audss-clock-controller@3810000 { | |
62 | compatible = "samsung,exynos5250-audss-clock"; | |
63 | reg = <0x03810000 0x0C>; | |
64 | #clock-cells = <1>; | |
65 | }; | |
66 | ||
67 | Example 2: An example of a clock controller node with the input clocks | |
68 | specified. | |
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69 | |
70 | clock_audss: audss-clock-controller@3810000 { | |
71 | compatible = "samsung,exynos5250-audss-clock"; | |
72 | reg = <0x03810000 0x0C>; | |
73 | #clock-cells = <1>; | |
547f3350 AB |
74 | clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, |
75 | <&ext_i2s_clk>; | |
76 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; | |
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77 | }; |
78 | ||
547f3350 | 79 | Example 3: I2S controller node that consumes the clock generated by the clock |
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80 | controller. Refer to the standard clock bindings for information |
81 | about 'clocks' and 'clock-names' property. | |
82 | ||
83 | i2s0: i2s@03830000 { | |
84 | compatible = "samsung,i2s-v5"; | |
85 | reg = <0x03830000 0x100>; | |
86 | dmas = <&pdma0 10 | |
87 | &pdma0 9 | |
88 | &pdma0 8>; | |
89 | dma-names = "tx", "rx", "tx-sec"; | |
90 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | |
91 | <&clock_audss EXYNOS_I2S_BUS>, | |
92 | <&clock_audss EXYNOS_SCLK_I2S>, | |
93 | <&clock_audss EXYNOS_MOUT_AUDSS>, | |
94 | <&clock_audss EXYNOS_MOUT_I2S>; | |
95 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1", | |
2ec865b7 | 96 | "mout_audss", "mout_i2s"; |
1241ef94 | 97 | }; |