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Commit | Line | Data |
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0e87e043 SG |
1 | * Clock bindings for Freescale i.MX6 Quad |
2 | ||
3 | Required properties: | |
4 | - compatible: Should be "fsl,imx6q-ccm" | |
5 | - reg: Address and length of the register set | |
6 | - interrupts: Should contain CCM interrupt | |
7 | - #clock-cells: Should be <1> | |
8 | ||
9 | The clock consumer should specify the desired clock by having the clock | |
10 | ID in its "clocks" phandle cell. The following is a full list of i.MX6Q | |
11 | clocks and IDs. | |
12 | ||
13 | Clock ID | |
14 | --------------------------- | |
15 | dummy 0 | |
16 | ckil 1 | |
17 | ckih 2 | |
18 | osc 3 | |
19 | pll2_pfd0_352m 4 | |
20 | pll2_pfd1_594m 5 | |
21 | pll2_pfd2_396m 6 | |
22 | pll3_pfd0_720m 7 | |
23 | pll3_pfd1_540m 8 | |
24 | pll3_pfd2_508m 9 | |
25 | pll3_pfd3_454m 10 | |
26 | pll2_198m 11 | |
27 | pll3_120m 12 | |
28 | pll3_80m 13 | |
29 | pll3_60m 14 | |
30 | twd 15 | |
31 | step 16 | |
32 | pll1_sw 17 | |
33 | periph_pre 18 | |
34 | periph2_pre 19 | |
35 | periph_clk2_sel 20 | |
36 | periph2_clk2_sel 21 | |
37 | axi_sel 22 | |
38 | esai_sel 23 | |
39 | asrc_sel 24 | |
40 | spdif_sel 25 | |
41 | gpu2d_axi 26 | |
42 | gpu3d_axi 27 | |
43 | gpu2d_core_sel 28 | |
44 | gpu3d_core_sel 29 | |
45 | gpu3d_shader_sel 30 | |
46 | ipu1_sel 31 | |
47 | ipu2_sel 32 | |
48 | ldb_di0_sel 33 | |
49 | ldb_di1_sel 34 | |
50 | ipu1_di0_pre_sel 35 | |
51 | ipu1_di1_pre_sel 36 | |
52 | ipu2_di0_pre_sel 37 | |
53 | ipu2_di1_pre_sel 38 | |
54 | ipu1_di0_sel 39 | |
55 | ipu1_di1_sel 40 | |
56 | ipu2_di0_sel 41 | |
57 | ipu2_di1_sel 42 | |
58 | hsi_tx_sel 43 | |
59 | pcie_axi_sel 44 | |
60 | ssi1_sel 45 | |
61 | ssi2_sel 46 | |
62 | ssi3_sel 47 | |
63 | usdhc1_sel 48 | |
64 | usdhc2_sel 49 | |
65 | usdhc3_sel 50 | |
66 | usdhc4_sel 51 | |
67 | enfc_sel 52 | |
68 | emi_sel 53 | |
69 | emi_slow_sel 54 | |
70 | vdo_axi_sel 55 | |
71 | vpu_axi_sel 56 | |
72 | cko1_sel 57 | |
73 | periph 58 | |
74 | periph2 59 | |
75 | periph_clk2 60 | |
76 | periph2_clk2 61 | |
77 | ipg 62 | |
78 | ipg_per 63 | |
79 | esai_pred 64 | |
80 | esai_podf 65 | |
81 | asrc_pred 66 | |
82 | asrc_podf 67 | |
83 | spdif_pred 68 | |
84 | spdif_podf 69 | |
85 | can_root 70 | |
86 | ecspi_root 71 | |
87 | gpu2d_core_podf 72 | |
88 | gpu3d_core_podf 73 | |
89 | gpu3d_shader 74 | |
90 | ipu1_podf 75 | |
91 | ipu2_podf 76 | |
92 | ldb_di0_podf 77 | |
93 | ldb_di1_podf 78 | |
94 | ipu1_di0_pre 79 | |
95 | ipu1_di1_pre 80 | |
96 | ipu2_di0_pre 81 | |
97 | ipu2_di1_pre 82 | |
98 | hsi_tx_podf 83 | |
99 | ssi1_pred 84 | |
100 | ssi1_podf 85 | |
101 | ssi2_pred 86 | |
102 | ssi2_podf 87 | |
103 | ssi3_pred 88 | |
104 | ssi3_podf 89 | |
105 | uart_serial_podf 90 | |
106 | usdhc1_podf 91 | |
107 | usdhc2_podf 92 | |
108 | usdhc3_podf 93 | |
109 | usdhc4_podf 94 | |
110 | enfc_pred 95 | |
111 | enfc_podf 96 | |
112 | emi_podf 97 | |
113 | emi_slow_podf 98 | |
114 | vpu_axi_podf 99 | |
115 | cko1_podf 100 | |
116 | axi 101 | |
117 | mmdc_ch0_axi_podf 102 | |
118 | mmdc_ch1_axi_podf 103 | |
119 | arm 104 | |
120 | ahb 105 | |
121 | apbh_dma 106 | |
122 | asrc 107 | |
123 | can1_ipg 108 | |
124 | can1_serial 109 | |
125 | can2_ipg 110 | |
126 | can2_serial 111 | |
127 | ecspi1 112 | |
128 | ecspi2 113 | |
129 | ecspi3 114 | |
130 | ecspi4 115 | |
131 | ecspi5 116 | |
132 | enet 117 | |
133 | esai 118 | |
134 | gpt_ipg 119 | |
135 | gpt_ipg_per 120 | |
136 | gpu2d_core 121 | |
137 | gpu3d_core 122 | |
138 | hdmi_iahb 123 | |
139 | hdmi_isfr 124 | |
140 | i2c1 125 | |
141 | i2c2 126 | |
142 | i2c3 127 | |
143 | iim 128 | |
144 | enfc 129 | |
145 | ipu1 130 | |
146 | ipu1_di0 131 | |
147 | ipu1_di1 132 | |
148 | ipu2 133 | |
149 | ipu2_di0 134 | |
150 | ldb_di0 135 | |
151 | ldb_di1 136 | |
152 | ipu2_di1 137 | |
153 | hsi_tx 138 | |
154 | mlb 139 | |
155 | mmdc_ch0_axi 140 | |
156 | mmdc_ch1_axi 141 | |
157 | ocram 142 | |
158 | openvg_axi 143 | |
159 | pcie_axi 144 | |
160 | pwm1 145 | |
161 | pwm2 146 | |
162 | pwm3 147 | |
163 | pwm4 148 | |
164 | per1_bch 149 | |
165 | gpmi_bch_apb 150 | |
166 | gpmi_bch 151 | |
167 | gpmi_io 152 | |
168 | gpmi_apb 153 | |
169 | sata 154 | |
170 | sdma 155 | |
171 | spba 156 | |
172 | ssi1 157 | |
173 | ssi2 158 | |
174 | ssi3 159 | |
175 | uart_ipg 160 | |
176 | uart_serial 161 | |
177 | usboh3 162 | |
178 | usdhc1 163 | |
179 | usdhc2 164 | |
180 | usdhc3 165 | |
181 | usdhc4 166 | |
182 | vdo_axi 167 | |
183 | vpu_axi 168 | |
184 | cko1 169 | |
185 | pll1_sys 170 | |
186 | pll2_bus 171 | |
187 | pll3_usb_otg 172 | |
188 | pll4_audio 173 | |
189 | pll5_video 174 | |
13861701 | 190 | pll8_mlb 175 |
0e87e043 | 191 | pll7_usb_host 176 |
13861701 | 192 | pll6_enet 177 |
0e87e043 SG |
193 | ssi1_ipg 178 |
194 | ssi2_ipg 179 | |
195 | ssi3_ipg 180 | |
196 | rom 181 | |
197 | usbphy1 182 | |
198 | usbphy2 183 | |
199 | ldb_di0_div_3_5 184 | |
200 | ldb_di1_div_3_5 185 | |
7a04092c SH |
201 | sata_ref 186 |
202 | sata_ref_100m 187 | |
203 | pcie_ref 188 | |
204 | pcie_ref_125m 189 | |
205 | enet_ref 190 | |
a5120e89 PC |
206 | usbphy1_gate 191 |
207 | usbphy2_gate 192 | |
2df1d026 PZ |
208 | pll4_post_div 193 |
209 | pll5_post_div 194 | |
210 | pll5_video_div 195 | |
9545b2ed | 211 | eim_slow 196 |
1fa5007b | 212 | spdif 197 |
6526bb3c SG |
213 | cko2_sel 198 |
214 | cko2_podf 199 | |
215 | cko2 200 | |
0e87e043 SG |
216 | |
217 | Examples: | |
218 | ||
219 | clks: ccm@020c4000 { | |
220 | compatible = "fsl,imx6q-ccm"; | |
221 | reg = <0x020c4000 0x4000>; | |
222 | interrupts = <0 87 0x04 0 88 0x04>; | |
223 | #clock-cells = <1>; | |
0e87e043 SG |
224 | }; |
225 | ||
226 | uart1: serial@02020000 { | |
227 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | |
228 | reg = <0x02020000 0x4000>; | |
229 | interrupts = <0 26 0x04>; | |
230 | clocks = <&clks 160>, <&clks 161>; | |
231 | clock-names = "ipg", "per"; | |
232 | status = "disabled"; | |
233 | }; |