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Commit | Line | Data |
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7b42a997 SH |
1 | * Renesas R8A7779 Clock Pulse Generator (CPG) |
2 | ||
3 | The CPG generates core clocks for the R8A7779. It includes one PLL and | |
b31fc90c GU |
4 | several fixed ratio dividers. |
5 | The CPG also provides a Clock Domain for SoC devices, in combination with the | |
6 | CPG Module Stop (MSTP) Clocks. | |
7b42a997 SH |
7 | |
8 | Required Properties: | |
9 | ||
10 | - compatible: Must be "renesas,r8a7779-cpg-clocks" | |
11 | - reg: Base address and length of the memory resource used by the CPG | |
12 | ||
13 | - clocks: Reference to the parent clock | |
14 | - #clock-cells: Must be 1 | |
15 | - clock-output-names: The names of the clocks. Supported clocks are "plla", | |
16 | "z", "zs", "s", "s1", "p", "b", "out". | |
b31fc90c | 17 | - #power-domain-cells: Must be 0 |
7b42a997 | 18 | |
b31fc90c GU |
19 | SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed |
20 | through an MSTP clock should refer to the CPG device node in their | |
21 | "power-domains" property, as documented by the generic PM domain bindings in | |
22 | Documentation/devicetree/bindings/power/power_domain.txt. | |
7b42a997 | 23 | |
b31fc90c GU |
24 | |
25 | Examples | |
26 | -------- | |
27 | ||
28 | - CPG device node: | |
7b42a997 SH |
29 | |
30 | cpg_clocks: cpg_clocks@ffc80000 { | |
31 | compatible = "renesas,r8a7779-cpg-clocks"; | |
b31fc90c | 32 | reg = <0xffc80000 0x30>; |
7b42a997 SH |
33 | clocks = <&extal_clk>; |
34 | #clock-cells = <1>; | |
35 | clock-output-names = "plla", "z", "zs", "s", "s1", "p", | |
36 | "b", "out"; | |
b31fc90c GU |
37 | #power-domain-cells = <0>; |
38 | }; | |
39 | ||
40 | ||
41 | - CPG/MSTP Clock Domain member device node: | |
42 | ||
43 | sata: sata@fc600000 { | |
44 | compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; | |
45 | reg = <0xfc600000 0x2000>; | |
46 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | |
47 | clocks = <&mstp1_clks R8A7779_CLK_SATA>; | |
48 | power-domains = <&cpg_clocks>; | |
7b42a997 | 49 | }; |