]>
Commit | Line | Data |
---|---|---|
485a40d7 XZ |
1 | * Rockchip RK3399 Clock and Reset Unit |
2 | ||
3 | The RK3399 clock controller generates and supplies clock to various | |
4 | controllers within the SoC and also implements a reset controller for SoC | |
5 | peripherals. | |
6 | ||
7 | Required Properties: | |
8 | ||
9 | - compatible: PMU for CRU should be "rockchip,rk3399-pmucru" | |
10 | - compatible: CRU should be "rockchip,rk3399-cru" | |
11 | - reg: physical base address of the controller and length of memory mapped | |
12 | region. | |
13 | - #clock-cells: should be 1. | |
14 | - #reset-cells: should be 1. | |
15 | ||
16 | Each clock is assigned an identifier and client nodes can use this identifier | |
17 | to specify the clock which they consume. All available clocks are defined as | |
18 | preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be | |
19 | used in device tree sources. Similar macros exist for the reset sources in | |
20 | these files. | |
21 | ||
22 | External clocks: | |
23 | ||
24 | There are several clocks that are generated outside the SoC. It is expected | |
25 | that they are defined using standard clock bindings with following | |
26 | clock-output-names: | |
27 | - "xin24m" - crystal input - required, | |
28 | - "xin32k" - rtc clock - optional, | |
29 | - "clkin_gmac" - external GMAC clock - optional, | |
30 | - "clkin_i2s" - external I2S clock - optional, | |
31 | - "pclkin_cif" - external ISP clock - optional, | |
32 | - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 | |
33 | - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 | |
34 | ||
35 | Example: Clock controller node: | |
36 | ||
37 | pmucru: pmu-clock-controller@ff750000 { | |
38 | compatible = "rockchip,rk3399-pmucru"; | |
39 | reg = <0x0 0xff750000 0x0 0x1000>; | |
40 | #clock-cells = <1>; | |
41 | #reset-cells = <1>; | |
42 | }; | |
43 | ||
44 | cru: clock-controller@ff760000 { | |
45 | compatible = "rockchip,rk3399-cru"; | |
46 | reg = <0x0 0xff760000 0x0 0x1000>; | |
47 | #clock-cells = <1>; | |
48 | #reset-cells = <1>; | |
49 | }; | |
50 | ||
51 | Example: UART controller node that consumes the clock generated by the clock | |
52 | controller: | |
53 | ||
54 | uart0: serial@ff1a0000 { | |
55 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
56 | reg = <0x0 0xff180000 0x0 0x100>; | |
57 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
58 | clock-names = "baudclk", "apb_pclk"; | |
59 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
60 | reg-shift = <2>; | |
61 | reg-io-width = <4>; | |
62 | }; |