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Commit | Line | Data |
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ef6eb322 LW |
1 | ST Microelectronics Nomadik SRC System Reset and Control |
2 | ||
3 | This binding uses the common clock binding: | |
4 | Documentation/devicetree/bindings/clock/clock-bindings.txt | |
5 | ||
6 | The Nomadik SRC controller is responsible of controlling chrystals, | |
7 | PLLs and clock gates. | |
8 | ||
9 | Required properties for the SRC node: | |
10 | - compatible: must be "stericsson,nomadik-src" | |
11 | - reg: must contain the SRC register base and size | |
12 | ||
13 | Optional properties for the SRC node: | |
14 | - disable-sxtalo: if present this will disable the SXTALO | |
15 | i.e. the driver output for the slow 32kHz chrystal, if the | |
16 | board has its own circuitry for providing this oscillator | |
17 | - disable-mxtal: if present this will disable the MXTALO, | |
18 | i.e. the driver output for the main (~19.2 MHz) chrystal, | |
19 | if the board has its own circuitry for providing this | |
3999debe | 20 | oscillator |
ef6eb322 LW |
21 | |
22 | ||
23 | PLL nodes: these nodes represent the two PLLs on the system, | |
24 | which should both have the main chrystal, represented as a | |
25 | fixed frequency clock, as parent. | |
26 | ||
27 | Required properties for the two PLL nodes: | |
28 | - compatible: must be "st,nomadik-pll-clock" | |
29 | - clock-cells: must be 0 | |
30 | - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively | |
31 | - clocks: this clock will have main chrystal as parent | |
32 | ||
33 | ||
34 | HCLK nodes: these represent the clock gates on individual | |
35 | lines from the HCLK clock tree and the gate for individual | |
36 | lines from the PCLK clock tree. | |
37 | ||
38 | Requires properties for the HCLK nodes: | |
39 | - compatible: must be "st,nomadik-hclk-clock" | |
40 | - clock-cells: must be 0 | |
41 | - clock-id: must be the clock ID from 0 to 63 according to | |
42 | this table: | |
43 | ||
44 | 0: HCLKDMA0 | |
45 | 1: HCLKSMC | |
46 | 2: HCLKSDRAM | |
47 | 3: HCLKDMA1 | |
48 | 4: HCLKCLCD | |
49 | 5: PCLKIRDA | |
50 | 6: PCLKSSP | |
51 | 7: PCLKUART0 | |
52 | 8: PCLKSDI | |
53 | 9: PCLKI2C0 | |
54 | 10: PCLKI2C1 | |
55 | 11: PCLKUART1 | |
56 | 12: PCLMSP0 | |
57 | 13: HCLKUSB | |
58 | 14: HCLKDIF | |
59 | 15: HCLKSAA | |
60 | 16: HCLKSVA | |
61 | 17: PCLKHSI | |
62 | 18: PCLKXTI | |
63 | 19: PCLKUART2 | |
64 | 20: PCLKMSP1 | |
65 | 21: PCLKMSP2 | |
66 | 22: PCLKOWM | |
67 | 23: HCLKHPI | |
68 | 24: PCLKSKE | |
69 | 25: PCLKHSEM | |
70 | 26: HCLK3D | |
71 | 27: HCLKHASH | |
72 | 28: HCLKCRYP | |
73 | 29: PCLKMSHC | |
74 | 30: HCLKUSBM | |
75 | 31: HCLKRNG | |
76 | (32, 33, 34, 35 RESERVED) | |
77 | 36: CLDCLK | |
78 | 37: IRDACLK | |
79 | 38: SSPICLK | |
80 | 39: UART0CLK | |
81 | 40: SDICLK | |
82 | 41: I2C0CLK | |
83 | 42: I2C1CLK | |
84 | 43: UART1CLK | |
85 | 44: MSPCLK0 | |
86 | 45: USBCLK | |
87 | 46: DIFCLK | |
88 | 47: IPI2CCLK | |
89 | 48: IPBMCCLK | |
90 | 49: HSICLKRX | |
91 | 50: HSICLKTX | |
92 | 51: UART2CLK | |
93 | 52: MSPCLK1 | |
94 | 53: MSPCLK2 | |
95 | 54: OWMCLK | |
96 | (55 RESERVED) | |
97 | 56: SKECLK | |
98 | (57 RESERVED) | |
99 | 58: 3DCLK | |
100 | 59: PCLKMSP3 | |
101 | 60: MSPCLK3 | |
102 | 61: MSHCCLK | |
103 | 62: USBMCLK | |
104 | 63: RNGCCLK |