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Commit | Line | Data |
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e874a669 EL |
1 | Device Tree Clock bindings for arch-sunxi |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | Required properties: | |
8 | - compatible : shall be one of the following: | |
e3276998 | 9 | "allwinner,sun4i-osc-clk" - for a gatable oscillator |
d838ff33 | 10 | "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4 |
6a721db1 | 11 | "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 |
e3276998 EL |
12 | "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock |
13 | "allwinner,sun4i-axi-clk" - for the AXI clock | |
13569a70 | 14 | "allwinner,sun4i-axi-gates-clk" - for the AXI gates |
e3276998 | 15 | "allwinner,sun4i-ahb-clk" - for the AHB clock |
4f985b4c MR |
16 | "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 |
17 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 | |
2371dd88 | 18 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
1fb2e4aa | 19 | "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 |
6a721db1 MR |
20 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 |
21 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 | |
e3276998 | 22 | "allwinner,sun4i-apb0-clk" - for the APB0 clock |
4f985b4c MR |
23 | "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 |
24 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 | |
2371dd88 | 25 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
1fb2e4aa | 26 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
e3276998 EL |
27 | "allwinner,sun4i-apb1-clk" - for the APB1 clock |
28 | "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing | |
4f985b4c MR |
29 | "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 |
30 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 | |
2371dd88 | 31 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
6a721db1 | 32 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
1fb2e4aa | 33 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
6a721db1 MR |
34 | "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 |
35 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 | |
e874a669 EL |
36 | |
37 | Required properties for all clocks: | |
38 | - reg : shall be the control register address for the clock. | |
39 | - clocks : shall be the input parent clock(s) phandle for the clock | |
13569a70 | 40 | - #clock-cells : from common clock binding; shall be set to 0 except for |
4f985b4c | 41 | "allwinner,*-gates-clk" where it shall be set to 1 |
13569a70 | 42 | |
4f985b4c | 43 | Additionally, "allwinner,*-gates-clk" clocks require: |
13569a70 | 44 | - clock-output-names : the corresponding gate names that the clock controls |
e874a669 | 45 | |
4f985b4c MR |
46 | Clock consumers should specify the desired clocks they use with a |
47 | "clocks" phandle cell. Consumers that are using a gated clock should | |
fc42ef51 MR |
48 | provide an additional ID in their clock property. This ID is the |
49 | offset of the bit controlling this particular gate in the register. | |
4f985b4c | 50 | |
e874a669 EL |
51 | For example: |
52 | ||
53 | osc24M: osc24M@01c20050 { | |
54 | #clock-cells = <0>; | |
e3276998 | 55 | compatible = "allwinner,sun4i-osc-clk"; |
e874a669 EL |
56 | reg = <0x01c20050 0x4>; |
57 | clocks = <&osc24M_fixed>; | |
58 | }; | |
59 | ||
60 | pll1: pll1@01c20000 { | |
61 | #clock-cells = <0>; | |
e3276998 | 62 | compatible = "allwinner,sun4i-pll1-clk"; |
e874a669 EL |
63 | reg = <0x01c20000 0x4>; |
64 | clocks = <&osc24M>; | |
65 | }; | |
66 | ||
67 | cpu: cpu@01c20054 { | |
68 | #clock-cells = <0>; | |
e3276998 | 69 | compatible = "allwinner,sun4i-cpu-clk"; |
e874a669 EL |
70 | reg = <0x01c20054 0x4>; |
71 | clocks = <&osc32k>, <&osc24M>, <&pll1>; | |
72 | }; |