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Commit | Line | Data |
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e874a669 EL |
1 | Device Tree Clock bindings for arch-sunxi |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | Required properties: | |
8 | - compatible : shall be one of the following: | |
fd1b22f6 MR |
9 | "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator |
10 | "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 | |
6a721db1 | 11 | "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 |
515c1a4b | 12 | "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 |
3b2bd70f | 13 | "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 |
fd1b22f6 MR |
14 | "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock |
15 | "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock | |
92ef67c5 | 16 | "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 |
3b2bd70f | 17 | "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 |
fd1b22f6 MR |
18 | "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock |
19 | "allwinner,sun4i-a10-axi-clk" - for the AXI clock | |
515c1a4b | 20 | "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 |
fd1b22f6 MR |
21 | "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates |
22 | "allwinner,sun4i-a10-ahb-clk" - for the AHB clock | |
3b2bd70f | 23 | "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 |
fd1b22f6 | 24 | "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 |
4f985b4c | 25 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 |
2371dd88 | 26 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
1fb2e4aa | 27 | "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 |
5c89a8b6 | 28 | "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 |
7954dfae | 29 | "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 |
6a721db1 | 30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
515c1a4b | 31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
0b0f0802 CYT |
32 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 |
33 | "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 | |
34 | "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 | |
fd1b22f6 | 35 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock |
5c89a8b6 | 36 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 |
57a1fbf2 | 37 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 |
3b2bd70f | 38 | "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 |
fd1b22f6 | 39 | "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 |
4f985b4c | 40 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 |
2371dd88 | 41 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
5c89a8b6 | 42 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 |
1fb2e4aa | 43 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
6c1d66f0 | 44 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 |
0b0f0802 | 45 | "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 |
fd1b22f6 | 46 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock |
3b2bd70f | 47 | "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 |
fd1b22f6 | 48 | "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 |
4f985b4c | 49 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 |
2371dd88 | 50 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
6a721db1 | 51 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
1fb2e4aa | 52 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
515c1a4b | 53 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 |
0b0f0802 | 54 | "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 |
6a721db1 | 55 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
515c1a4b | 56 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |
03e29bbf | 57 | "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 |
37e1041f MR |
58 | "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 |
59 | "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 | |
fd1b22f6 | 60 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks |
9c8176bf | 61 | "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 |
6f863417 | 62 | "allwinner,sun7i-a20-out-clk" - for the external output clocks |
e4c6d6c1 | 63 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 |
5abdbf2f RB |
64 | "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 |
65 | "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 | |
6d1d14d5 | 66 | "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 |
e874a669 EL |
67 | |
68 | Required properties for all clocks: | |
69 | - reg : shall be the control register address for the clock. | |
7551769a EL |
70 | - clocks : shall be the input parent clock(s) phandle for the clock. For |
71 | multiplexed clocks, the list order must match the hardware | |
72 | programming order. | |
13569a70 | 73 | - #clock-cells : from common clock binding; shall be set to 0 except for |
95e94c1f CYT |
74 | the following compatibles where it shall be set to 1: |
75 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", | |
76 | "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk" | |
373d4e6b CYT |
77 | - clock-output-names : shall be the corresponding names of the outputs. |
78 | If the clock module only has one output, the name shall be the | |
79 | module name. | |
e874a669 | 80 | |
5abdbf2f RB |
81 | And "allwinner,*-usb-clk" clocks also require: |
82 | - reset-cells : shall be set to 1 | |
83 | ||
e4c6d6c1 CYT |
84 | For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate |
85 | dummy clocks at 25 MHz and 125 MHz, respectively. See example. | |
86 | ||
4f985b4c MR |
87 | Clock consumers should specify the desired clocks they use with a |
88 | "clocks" phandle cell. Consumers that are using a gated clock should | |
fc42ef51 MR |
89 | provide an additional ID in their clock property. This ID is the |
90 | offset of the bit controlling this particular gate in the register. | |
95e94c1f CYT |
91 | For the other clocks with "#clock-cells" = 1, the additional ID shall |
92 | refer to the index of the output. | |
93 | ||
94 | For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output | |
95 | is the normal PLL6 output, or "pll6". The second output is rate doubled | |
96 | PLL6, or "pll6x2". | |
4f985b4c | 97 | |
e874a669 EL |
98 | For example: |
99 | ||
373d4e6b | 100 | osc24M: clk@01c20050 { |
e874a669 | 101 | #clock-cells = <0>; |
fd1b22f6 | 102 | compatible = "allwinner,sun4i-a10-osc-clk"; |
e874a669 EL |
103 | reg = <0x01c20050 0x4>; |
104 | clocks = <&osc24M_fixed>; | |
373d4e6b | 105 | clock-output-names = "osc24M"; |
e874a669 EL |
106 | }; |
107 | ||
373d4e6b | 108 | pll1: clk@01c20000 { |
e874a669 | 109 | #clock-cells = <0>; |
fd1b22f6 | 110 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
e874a669 EL |
111 | reg = <0x01c20000 0x4>; |
112 | clocks = <&osc24M>; | |
373d4e6b CYT |
113 | clock-output-names = "pll1"; |
114 | }; | |
115 | ||
116 | pll5: clk@01c20020 { | |
117 | #clock-cells = <1>; | |
118 | compatible = "allwinner,sun4i-pll5-clk"; | |
119 | reg = <0x01c20020 0x4>; | |
120 | clocks = <&osc24M>; | |
121 | clock-output-names = "pll5_ddr", "pll5_other"; | |
e874a669 EL |
122 | }; |
123 | ||
95e94c1f CYT |
124 | pll6: clk@01c20028 { |
125 | #clock-cells = <1>; | |
126 | compatible = "allwinner,sun6i-a31-pll6-clk"; | |
127 | reg = <0x01c20028 0x4>; | |
128 | clocks = <&osc24M>; | |
129 | clock-output-names = "pll6", "pll6x2"; | |
130 | }; | |
131 | ||
e874a669 EL |
132 | cpu: cpu@01c20054 { |
133 | #clock-cells = <0>; | |
fd1b22f6 | 134 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
e874a669 EL |
135 | reg = <0x01c20054 0x4>; |
136 | clocks = <&osc32k>, <&osc24M>, <&pll1>; | |
373d4e6b CYT |
137 | clock-output-names = "cpu"; |
138 | }; | |
139 | ||
140 | mmc0_clk: clk@01c20088 { | |
141 | #clock-cells = <0>; | |
142 | compatible = "allwinner,sun4i-mod0-clk"; | |
143 | reg = <0x01c20088 0x4>; | |
144 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
145 | clock-output-names = "mmc0"; | |
e874a669 | 146 | }; |
e4c6d6c1 CYT |
147 | |
148 | mii_phy_tx_clk: clk@2 { | |
149 | #clock-cells = <0>; | |
150 | compatible = "fixed-clock"; | |
151 | clock-frequency = <25000000>; | |
152 | clock-output-names = "mii_phy_tx"; | |
153 | }; | |
154 | ||
155 | gmac_int_tx_clk: clk@3 { | |
156 | #clock-cells = <0>; | |
157 | compatible = "fixed-clock"; | |
158 | clock-frequency = <125000000>; | |
159 | clock-output-names = "gmac_int_tx"; | |
160 | }; | |
161 | ||
162 | gmac_clk: clk@01c20164 { | |
163 | #clock-cells = <0>; | |
164 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
165 | reg = <0x01c20164 0x4>; | |
166 | /* | |
167 | * The first clock must be fixed at 25MHz; | |
168 | * the second clock must be fixed at 125MHz | |
169 | */ | |
170 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
171 | clock-output-names = "gmac"; | |
172 | }; |